Attention is currently required from: Sean Rhodes, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62990 )
Change subject: drivers/smmstore: Enable 4KiB blocks in SMMSTORE ......................................................................
Patch Set 1:
(2 comments)
Patchset:
PS1:
See https://github.com/coreboot/coreboot/blob/1f54599b9875e0de80c8636626bdfbe016...
Not sure what the minimum flash sector size is on AMD or older platforms. Maybe this can be gathered from Kconfig/bootmedia API?
It depends on the coreboot driver for the flash chip see 'sector_size_kib_shift'. 64K is the smallest common denomination.
PS1:
It's this^ change, or this -https://github.com/StarLabsLtd/edk2/commit/e5033f0e9a01c2d4288370ef25cb12f2e...
I'm not sure I understand that patch. It just looks like the block alignment check is broken in EDK2 and that 4K writes is just a workaround.
The suggestion came from Patrick, to avoid the edk2 patches. It does not break erasing.
That depends on the flash chip you have installed. spi_flash_cmd_erase() will check the block erase size against the erase size arguments. So this would break some flash chips.