Hung-Te Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34772 )
Change subject: soc/mediatek: dsi: Refactor video timing calculation ......................................................................
soc/mediatek: dsi: Refactor video timing calculation
The video timing should be based on PHY timing. Some values can be ignored on 8173 because of fixed values in PHY but should be calculated for newer platforms like 8183.
BUG=b:80501386,b:117254947 TEST=make -j # board = oak and boots
Change-Id: Id3ad2edc08787414a74188f5050460e98222caf4 Signed-off-by: Hung-Te Lin hungte@chromium.org --- M src/soc/mediatek/common/dsi.c M src/soc/mediatek/mt8173/include/soc/dsi.h 2 files changed, 28 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/34772/1
diff --git a/src/soc/mediatek/common/dsi.c b/src/soc/mediatek/common/dsi.c index 84ddaa1..17b127a 100644 --- a/src/soc/mediatek/common/dsi.c +++ b/src/soc/mediatek/common/dsi.c @@ -141,8 +141,9 @@ write32(&dsi0->dsi_txrx_ctrl, tmp_reg); }
-static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format, - const struct edid *edid) +static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format, u32 lanes, + const struct edid *edid, + const struct mtk_phy_timing *phy_timing) { u32 hsync_active_byte; u32 hbp_byte; @@ -152,6 +153,7 @@ u32 bytes_per_pixel; u32 packet_fmt; u32 hactive; + u32 data_phy_cycles;
bytes_per_pixel = mtk_dsi_get_bits_per_pixel(format) / 8; vbp_byte = edid->mode.vbl - edid->mode.vso - edid->mode.vspw - @@ -163,15 +165,27 @@ write32(&dsi0->dsi_vfp_nl, vfp_byte); write32(&dsi0->dsi_vact_nl, edid->mode.va);
+ unsigned int hspw = 0; if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) - hbp_byte = (edid->mode.hbl - edid->mode.hso - edid->mode.hspw - - edid->mode.hborder) * bytes_per_pixel - 10; - else - hbp_byte = (edid->mode.hbl - edid->mode.hso - - edid->mode.hborder) * bytes_per_pixel - 10; + hspw = edid->mode.hspw;
+ hbp_byte = (edid->mode.hbl - edid->mode.hso - hspw - edid->mode.hborder) + * bytes_per_pixel - 10; hsync_active_byte = edid->mode.hspw * bytes_per_pixel - 10; - hfp_byte = (edid->mode.hso - edid->mode.hborder) * bytes_per_pixel - 12; + hfp_byte = (edid->mode.hso - edid->mode.hborder) * bytes_per_pixel; + + data_phy_cycles = phy_timing->lpx + phy_timing->da_hs_prepare + + phy_timing->da_hs_zero + phy_timing->da_hs_exit + 2; + + u32 delta = 12; + if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) + delta += 6; + + u32 d_phy = data_phy_cycles * lanes + delta; + if (hfp_byte > d_phy) + hfp_byte -= d_phy; + else + printk(BIOS_ERR, "HFP less than d-phy, FPS < 60Hz\n");
write32(&dsi0->dsi_hsa_wc, hsync_active_byte); write32(&dsi0->dsi_hbp_wc, hbp_byte); @@ -198,7 +212,8 @@ hactive = edid->mode.ha; packet_fmt |= (hactive * bytes_per_pixel) & DSI_PS_WC;
- write32(&dsi0->dsi_psctrl, packet_fmt); + write32(&dsi0->dsi_psctrl, + PIXEL_STREAM_CUSTOM_HEADER << 26 | packet_fmt); }
static void mtk_dsi_start(void) @@ -223,7 +238,7 @@ mtk_dsi_phy_timing(data_rate, &phy_timing); mtk_dsi_rxtx_control(mode_flags, lanes); mtk_dsi_clk_hs_mode_disable(); - mtk_dsi_config_vdo_timing(mode_flags, format, edid); + mtk_dsi_config_vdo_timing(mode_flags, format, lanes, edid, &phy_timing); mtk_dsi_set_mode(mode_flags); mtk_dsi_clk_hs_mode_enable();
diff --git a/src/soc/mediatek/mt8173/include/soc/dsi.h b/src/soc/mediatek/mt8173/include/soc/dsi.h index 4d87406..e57bfc5 100644 --- a/src/soc/mediatek/mt8173/include/soc/dsi.h +++ b/src/soc/mediatek/mt8173/include/soc/dsi.h @@ -130,7 +130,9 @@ PACKED_PS_16BIT_RGB565 = (0 << 16), LOOSELY_PS_18BIT_RGB666 = (1 << 16), PACKED_PS_18BIT_RGB666 = (2 << 16), - PACKED_PS_24BIT_RGB888 = (3 << 16) + PACKED_PS_24BIT_RGB888 = (3 << 16), + + PIXEL_STREAM_CUSTOM_HEADER = 0, };
/* DSI_CMDQ_SIZE */