2 Oct
2020
2 Oct
'20
10:53 a.m.
Masanori Ogino has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45914 )
Change subject: nb/intel/i945/memmap.c: Use `postcar_enable_tseg_cache` ......................................................................
Patch Set 2: Code-Review+1
The `postcar_enable_tseg_cache` function is essentially equivalent to the removed code block.
It compiles on top of commit a5f4781d81 with `CONFIG_TSEG_STAGE_CACHE=y` and `CONFIG_SMM_TSEG=y`, runs on Lenovo ThinkPad X60s, and boots Linux 5.4.68 with SeaBIOS 1.14.0 and GRUB 2.0.4.
It looks good to me.
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I5f3720c02875f546f9dad4bb5582e97d91d39c0d
Gerrit-Change-Number: 45914
Gerrit-PatchSet: 2
Gerrit-Owner: Angel Pons th3fanbus@gmail.com
Gerrit-Reviewer: Masanori Ogino mogino@acm.org
Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org
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Gerrit-CC: HAOUAS Elyes ehaouas@noos.fr
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Gerrit-Comment-Date: Fri, 02 Oct 2020 10:53:19 +0000
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