Felix Held has submitted this change and it was merged. ( https://review.coreboot.org/27667 )
Change subject: nb/intel/sandybridge/report_platform: Move remaining code to sb folder ......................................................................
nb/intel/sandybridge/report_platform: Move remaining code to sb folder
Change-Id: I2ced3f2bb9d1d150341a57ff333ca14c897c4fa3 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com Reviewed-on: https://review.coreboot.org/27667 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Felix Held felix-coreboot@felixheld.de --- M src/northbridge/intel/sandybridge/Makefile.inc M src/northbridge/intel/sandybridge/raminit.c D src/northbridge/intel/sandybridge/report_platform.c M src/northbridge/intel/sandybridge/sandybridge.h M src/southbridge/intel/bd82x6x/lpc.c 5 files changed, 71 insertions(+), 95 deletions(-)
Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved
diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index 9673cd1..304ea30 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -46,7 +46,6 @@ romstage-y += romstage.c romstage-y += iommu.c romstage-y += early_init.c -romstage-y += report_platform.c romstage-y += ../../../arch/x86/walkcbfs.S
smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index c0f9c6f..47474ee 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -323,8 +323,6 @@
MCHBAR32(0x5f00) |= 1;
- report_platform_info(); - /* Wait for ME to be ready */ intel_early_me_init(); me_uma_size = intel_early_me_uma_size(); diff --git a/src/northbridge/intel/sandybridge/report_platform.c b/src/northbridge/intel/sandybridge/report_platform.c deleted file mode 100644 index 7e647d8..0000000 --- a/src/northbridge/intel/sandybridge/report_platform.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <southbridge/intel/bd82x6x/pch.h> -#include "sandybridge.h" - -static struct { - u16 dev_id; - const char *dev_name; -} pch_table [] = { - /* 6-series PCI ids from - * Intel® 6 Series Chipset and - * Intel® C200 Series Chipset - * Specification Update - NDA - * October 2013 - * CDI / IBP#: 440377 - */ - {0x1C41, "SFF Sample"}, - {0x1C42, "Desktop Sample"}, - {0x1C43, "Mobile Sample"}, - {0x1C44, "Z68"}, - {0x1C46, "P67"}, - {0x1C47, "UM67"}, - {0x1C49, "HM65"}, - {0x1C4A, "H67"}, - {0x1C4B, "HM67"}, - {0x1C4C, "Q65"}, - {0x1C4D, "QS67"}, - {0x1C4E, "Q67"}, - {0x1C4F, "QM67"}, - {0x1C50, "B65"}, - {0x1C52, "C202"}, - {0x1C54, "C204"}, - {0x1C56, "C206"}, - {0x1C5C, "H61"}, - /* 7-series PCI ids from Intel document 472178 */ - {0x1E41, "Desktop Sample"}, - {0x1E42, "Mobile Sample"}, - {0x1E43, "SFF Sample"}, - {0x1E44, "Z77"}, - {0x1E45, "H71"}, - {0x1E46, "Z75"}, - {0x1E47, "Q77"}, - {0x1E48, "Q75"}, - {0x1E49, "B75"}, - {0x1E4A, "H77"}, - {0x1E53, "C216"}, - {0x1E55, "QM77"}, - {0x1E56, "QS77"}, - {0x1E58, "UM77"}, - {0x1E57, "HM77"}, - {0x1E59, "HM76"}, - {0x1E5D, "HM75"}, - {0x1E5E, "HM70"}, - {0x1E5F, "NM70"}, -}; - -static void report_pch_info(void) -{ - int i; - u16 dev_id = pci_read_config16(PCH_LPC_DEV, 2); - - - const char *pch_type = "Unknown"; - for (i = 0; i < ARRAY_SIZE(pch_table); i++) { - if (pch_table[i].dev_id == dev_id) { - pch_type = pch_table[i].dev_name; - break; - } - } - printk (BIOS_DEBUG, "PCH type: %s, device id: %x, rev id %x\n", - pch_type, dev_id, pci_read_config8(PCH_LPC_DEV, 8)); -} - -void report_platform_info(void) -{ - report_pch_info(); -} diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 3269605..693bfb7 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -217,7 +217,6 @@ void dump_pci_devices(void); void dump_spd_registers(void); void dump_mem(unsigned start, unsigned end); -void report_platform_info(void);
#endif /* !__SMM__ */
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 611b08f..d9e72b4 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -19,6 +19,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include <device/pci_def.h> #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> #include <pc80/i8259.h> @@ -500,10 +501,80 @@ RCBA32_OR(0x3800 + 0xc4, 1 << 23); /* lock both UVSCC + LVSCC */ }
+static const struct { + u16 dev_id; + const char *dev_name; +} pch_table[] = { + /* 6-series PCI ids from + * Intel® 6 Series Chipset and + * Intel® C200 Series Chipset + * Specification Update - NDA + * October 2013 + * CDI / IBP#: 440377 + */ + {0x1C41, "SFF Sample"}, + {0x1C42, "Desktop Sample"}, + {0x1C43, "Mobile Sample"}, + {0x1C44, "Z68"}, + {0x1C46, "P67"}, + {0x1C47, "UM67"}, + {0x1C49, "HM65"}, + {0x1C4A, "H67"}, + {0x1C4B, "HM67"}, + {0x1C4C, "Q65"}, + {0x1C4D, "QS67"}, + {0x1C4E, "Q67"}, + {0x1C4F, "QM67"}, + {0x1C50, "B65"}, + {0x1C52, "C202"}, + {0x1C54, "C204"}, + {0x1C56, "C206"}, + {0x1C5C, "H61"}, + /* 7-series PCI ids from Intel document 472178 */ + {0x1E41, "Desktop Sample"}, + {0x1E42, "Mobile Sample"}, + {0x1E43, "SFF Sample"}, + {0x1E44, "Z77"}, + {0x1E45, "H71"}, + {0x1E46, "Z75"}, + {0x1E47, "Q77"}, + {0x1E48, "Q75"}, + {0x1E49, "B75"}, + {0x1E4A, "H77"}, + {0x1E53, "C216"}, + {0x1E55, "QM77"}, + {0x1E56, "QS77"}, + {0x1E58, "UM77"}, + {0x1E57, "HM77"}, + {0x1E59, "HM76"}, + {0x1E5D, "HM75"}, + {0x1E5E, "HM70"}, + {0x1E5F, "NM70"}, +}; + +static void report_pch_info(struct device *dev) +{ + const u16 dev_id = pci_read_config16(dev, PCI_DEVICE_ID); + int i; + + const char *pch_type = "Unknown"; + for (i = 0; i < ARRAY_SIZE(pch_table); i++) { + if (pch_table[i].dev_id == dev_id) { + pch_type = pch_table[i].dev_name; + break; + } + } + printk(BIOS_INFO, "PCH: detected %s, device id: 0x%x, rev id 0x%x\n", + pch_type, dev_id, pci_read_config8(dev, PCI_CLASS_REVISION)); +} + static void lpc_init(struct device *dev) { printk(BIOS_DEBUG, "pch: lpc_init\n");
+ /* Print detected platform */ + report_pch_info(dev); + /* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f);