[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Add SMRR Locking support

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45013 )

Change subject: soc/intel/tigerlake: Add SMRR Locking support
......................................................................

soc/intel/tigerlake: Add SMRR Locking support

The SMRR MSRs can be locked, so that a further write to them will cause
a #GP.  This patch adds that functionality, but since the MSR is a
core-level register, it must only be done once per core; if the SoC has
hyperthreading enabled, then attempting to write the SMRR Lock bit on
the primary thread will cause a #GP when the secondary (sibling) thread
attempts to also write to this MSR.

BUG=b:164489598
TEST=Boot into OS, verify using `iotools rdmsr` that all threads have
the Lock bit set.

Signed-off-by: Tim Wawrzynczak 
Change-Id: I4ae7c7f703bdf090144637d071eb810617d9e309
---
M src/soc/intel/tigerlake/Kconfig
M src/soc/intel/tigerlake/smmrelocate.c
2 files changed, 9 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/45013/1

diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index 8718f97..eb0cb77 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -16,6 +16,7 @@
    select BOOT_DEVICE_SUPPORTS_WRITES
    select CACHE_MRC_SETTINGS
    select CPU_INTEL_COMMON
+	select CPU_INTEL_COMMON_HYPERTHREADING
    select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
    select FSP_COMPRESS_FSP_S_LZ4
    select FSP_M_XIP
diff --git a/src/soc/intel/tigerlake/smmrelocate.c b/src/soc/intel/tigerlake/smmrelocate.c
index bbdcb68..3dada3e 100644
--- a/src/soc/intel/tigerlake/smmrelocate.c
+++ b/src/soc/intel/tigerlake/smmrelocate.c
@@ -9,6 +9,7 @@
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/smm.h>
+#include <cpu/intel/common/common.h>
 #include <cpu/intel/em64t101_save_state.h>
 #include <cpu/intel/smm_reloc.h>
 #include <console/console.h>
@@ -139,7 +140,13 @@

/* Write SMRR MSRs based on indicated support. */
    mtrr_cap = rdmsr(MTRR_CAP_MSR);
-	if (mtrr_cap.lo & SMRR_SUPPORTED)
+
+	/* Set Lock bit if supported */
+	if (mtrr_cap.lo & SMRR_LOCK_SUPPORTED)
+		relo_params->mask.lo |= SMRR_PHYS_MASK_LOCK;
+
+	/* Write SMRRs (if supported) on each *core* only */
+	if ((mtrr_cap.lo & SMRR_SUPPORTED) && !intel_ht_sibling())
    	write_smrr(relo_params);
 }