[coreboot-gerrit] [XS] Change in coreboot[main]: sb/intel/bd82x6x/early_pch: Follow PCH BIOS spec

[Patrick Rudolph (Code Review)]

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78225?usp=email )

Change subject: sb/intel/bd82x6x/early_pch: Follow PCH BIOS spec
......................................................................

sb/intel/bd82x6x/early_pch: Follow PCH BIOS spec

PCH BIOS spec says that BIOS must clear BIT26 in register 0x338
in PEI, as done on lynxpoint.
Copy and adapt the lynxpoint code to do the same on bd82x6x.

Test: System still boots and all PCIe ports are fully working.

Change-Id: I865818c0c22194fffcb2bbdf8c43737b0dce2307
Signed-off-by: Patrick Rudolph 
---
M src/southbridge/intel/bd82x6x/early_pch.c
M src/southbridge/intel/bd82x6x/pch.h
2 files changed, 7 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/78225/1

diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c
index e4e002d..e5b0f3d 100644
--- a/src/southbridge/intel/bd82x6x/early_pch.c
+++ b/src/southbridge/intel/bd82x6x/early_pch.c
@@ -137,6 +137,9 @@
 {
    pci_write_config8(SOUTHBRIDGE, 0xa6, pci_read_config8(SOUTHBRIDGE, 0xa6) | 2);

+	for (uint8_t i = 0; i < 8; i++)
+		pci_update_config32(PCH_PCIE_DEV(i), 0x338, ~(1 << 26), 0);
+
    RCBA32(CIR1) = 0x00109000;
    RCBA32(REC); // !!! = 0x00000000
    RCBA32(REC) = 0x40000000;
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 8face06..6d164ea 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -74,12 +74,15 @@
 #define PCH_EHCI2_DEV		PCI_DEV(0, 0x1a, 0)
 #define PCH_ME_DEV		PCI_DEV(0, 0x16, 0)
 #define PCH_THERMAL_DEV		PCI_DEV(0, 0x1f, 6)
-#define PCH_PCIE_DEV_SLOT	28
 #define PCH_IOAPIC_PCI_BUS	250
 #define PCH_IOAPIC_PCI_SLOT	31
 #define PCH_HPET_PCI_BUS	250
 #define PCH_HPET_PCI_SLOT	15

+/* PCI Configuration Space (D28:F0): PCI2PCI */
+#define PCH_PCIE_DEV_SLOT	28
+#define PCH_PCIE_DEV(_func)	PCI_DEV(0, PCH_PCIE_DEV_SLOT, _func)
+
 /* PCI Configuration Space (D20:F0): xHCI */
 #define PCH_XHCI_DEV		PCI_DEV(0, 0x14, 0)