[coreboot-gerrit] Patch set updated for coreboot: b6baa28 cpu/intel: >= nehalem: add comments to msr finalize's

[Alexander Couzens]

Alexander Couzens ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8294

-gerrit

commit b6baa28dd5346a3039a491b26716e4db803035e2
Author: Alexander Couzens 
Date:   Wed Jan 28 01:51:04 2015 +0100

cpu/intel: >= nehalem: add comments to msr finalize's

Improve documentation of lock down MSRs in finalize().
    Most of these aren't documented in public MSRs.

Change-Id: I4fc47bb9b71bdd7907aae65fc18b419a17ae8547
    Signed-off-by: Alexander Couzens 
---
 src/cpu/intel/fsp_model_206ax/finalize.c | 8 ++++++++
 src/cpu/intel/haswell/finalize.c         | 8 ++++++++
 src/cpu/intel/model_2065x/finalize.c     | 9 ++++++++-
 src/cpu/intel/model_206ax/finalize.c     | 8 ++++++++
 4 files changed, 32 insertions(+), 1 deletion(-)

diff --git a/src/cpu/intel/fsp_model_206ax/finalize.c b/src/cpu/intel/fsp_model_206ax/finalize.c
index 4ed5d1e..760e1f0 100644
--- a/src/cpu/intel/fsp_model_206ax/finalize.c
+++ b/src/cpu/intel/fsp_model_206ax/finalize.c
@@ -43,6 +43,11 @@ static void msr_set_bit(unsigned reg, unsigned bit)

void intel_model_206ax_finalize_smm(void)
 {
+	/* Documentation based on "Sandy Bridge Processor Family BIOS Writer's Guide (BWG)"
+	 * Document Number 504790
+	 * Revision 1.6.0, June 2012 */
+
+	/* Lock C-State MSR */
    msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15);

/* Lock AES-NI only if supported */
@@ -67,6 +72,9 @@ void intel_model_206ax_finalize_smm(void)
    msr_set_bit(MSR_PP1_POWER_LIMIT, 31);
 #endif

+	/* Lock TM interupts - route thermal events to all processors */
    msr_set_bit(MSR_MISC_PWR_MGMT, 22);
+
+	/* Lock memory configuration to protect SMM */
    msr_set_bit(MSR_LT_LOCK_MEMORY, 0);
 }
diff --git a/src/cpu/intel/haswell/finalize.c b/src/cpu/intel/haswell/finalize.c
index 1731322..fdf771b 100644
--- a/src/cpu/intel/haswell/finalize.c
+++ b/src/cpu/intel/haswell/finalize.c
@@ -46,6 +46,11 @@ static void msr_set_bit(unsigned reg, unsigned bit)
 void intel_cpu_haswell_finalize_smm(void)
 {
 #if 0
+	/* Documentation based on "Sandy Bridge Processor Family BIOS Writer's Guide (BWG)"
+	 * Document Number 504790
+	 * Revision 1.6.0, June 2012 */
+
+	/* Lock C-State MSR */
    msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15);

/* Lock AES-NI only if supported */
@@ -70,7 +75,10 @@ void intel_cpu_haswell_finalize_smm(void)
    msr_set_bit(MSR_PP1_POWER_LIMIT, 31);
 #endif

+	/* Lock TM interupts - route thermal events to all processors */
    msr_set_bit(MSR_MISC_PWR_MGMT, 22);
+
+	/* Lock memory configuration to protect SMM */
    msr_set_bit(MSR_LT_LOCK_MEMORY, 0);
 #endif
 }
diff --git a/src/cpu/intel/model_2065x/finalize.c b/src/cpu/intel/model_2065x/finalize.c
index b37a84c..e78d24a 100644
--- a/src/cpu/intel/model_2065x/finalize.c
+++ b/src/cpu/intel/model_2065x/finalize.c
@@ -44,6 +44,11 @@ static void msr_set_bit(unsigned reg, unsigned bit)

void intel_model_2065x_finalize_smm(void)
 {
+	/* Documentation based on "Sandy Bridge Processor Family BIOS Writer's Guide (BWG)"
+	 * Document Number 504790
+	 * Revision 1.6.0, June 2012 */
+
+	/* Lock C-State MSR */
    msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15);

/* Lock AES-NI only if supported */
@@ -67,7 +72,9 @@ void intel_model_2065x_finalize_smm(void)
    msr_set_bit(MSR_PP0_POWER_LIMIT, 31);
    msr_set_bit(MSR_PP1_POWER_LIMIT, 31);
 #endif
-
+	/* Lock TM interupts - route thermal events to all processors */
    msr_set_bit(MSR_MISC_PWR_MGMT, 22);
+
+	/* Lock memory configuration to protect SMM */
    msr_set_bit(MSR_LT_LOCK_MEMORY, 0);
 }
diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c
index 2c215a4..625fcd4 100644
--- a/src/cpu/intel/model_206ax/finalize.c
+++ b/src/cpu/intel/model_206ax/finalize.c
@@ -44,6 +44,11 @@ static void msr_set_bit(unsigned reg, unsigned bit)

void intel_model_206ax_finalize_smm(void)
 {
+	/* Documentation based on "Sandy Bridge Processor Family BIOS Writer's Guide (BWG)"
+	* Document Number 504790
+	* Revision 1.6.0, June 2012 */
+
+	/* Lock C-State MSR */
    msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15);

/* Lock AES-NI only if supported */
@@ -68,6 +73,9 @@ void intel_model_206ax_finalize_smm(void)
    msr_set_bit(MSR_PP1_POWER_LIMIT, 31);
 #endif

+	/* Lock TM interupts - route thermal events to all processors */
    msr_set_bit(MSR_MISC_PWR_MGMT, 22);
+
+	/* Lock memory configuration to protect SMM */
    msr_set_bit(MSR_LT_LOCK_MEMORY, 0);
 }