[coreboot-gerrit] Change in coreboot[master]: soc/skylake/fsp: enable PCIe Advanced Error Reporting (AER) by default

[Michael Niewöhner (Code Review)]

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35745 )

Change subject: soc/skylake/fsp: enable PCIe Advanced Error Reporting (AER) by default
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Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/35745/1/src/soc/intel/skylake/chip_... 
File src/soc/intel/skylake/chip_fsp20.c:

https://review.coreboot.org/c/coreboot/+/35745/1/src/soc/intel/skylake/chip_... 
PS1, Line 300: CONFIG_MAX_ROOT_PORTS
> nit, how about ARRAY_SIZE() or sizeof()? I hate it to see when some external  […]

because PcieRpAdvancedErrorReporting has a size of 24 bytes in any case and the board may have 12, 20 or 24 ports