[coreboot-gerrit] Change in coreboot[master]: vc/amd/fsp/picasso: Sync FSP-S UPD header file

[Marshall Dawson (Code Review)]

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45113 )

Change subject: vc/amd/fsp/picasso: Sync FSP-S UPD header file
......................................................................

vc/amd/fsp/picasso: Sync FSP-S UPD header file

Cq-Depend: chrome-internal:3247431
BUG=b:167421913, b:166519072, b:159664044
TEST=Boot morphius
BRANCH=Zork

Signed-off-by: Marshall Dawson 
Change-Id: Ic85e1f457c8932d933d8645738de68319dbf375a
---
M src/vendorcode/amd/fsp/picasso/FspsUpd.h
1 file changed, 4 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/45113/1

diff --git a/src/vendorcode/amd/fsp/picasso/FspsUpd.h b/src/vendorcode/amd/fsp/picasso/FspsUpd.h
index 5adbb81..ccd4568 100644
--- a/src/vendorcode/amd/fsp/picasso/FspsUpd.h
+++ b/src/vendorcode/amd/fsp/picasso/FspsUpd.h
@@ -31,7 +31,10 @@
    /** Offset 0x011D**/	uint8_t                     unused3;
    /** Offset 0x011E**/	uint32_t                    xhci_oc_pin_select;
    /** Offset 0x0122**/	uint8_t                     xhci0_force_gen1;
-	/** Offset 0x0123**/	uint8_t                     UnusedUpdSpace0[45];
+	/** Offset 0x0123**/	uint8_t                     xhci_sparse_mode_enable;
+	/** Offset 0x0124**/	uint8_t                     fch_ioapic_id;
+	/** Offset 0x0125**/	uint8_t                     gnb_ioapic_id;
+	/** Offset 0x0126**/	uint8_t                     UnusedUpdSpace0[42];
    /** Offset 0x0150**/	uint16_t                    UpdTerminator;
 } FSP_S_CONFIG;