[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Add eMMC PCR Port ID for Alder Lake N

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61126 )

Change subject: soc/intel/alderlake: Add eMMC PCR Port ID for Alder Lake N
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soc/intel/alderlake: Add eMMC PCR Port ID for Alder Lake N

Alder Lake N has eMMC storage device. Add PCR Port ID for it.
Reference: Alder Lake N platform EDS Doc# 645548.

Change-Id: I6dc494d1748e66b8b4058954f127ec226863e8af
Signed-off-by: Krishna Prasad Bhat 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61126
Tested-by: build bot (Jenkins) 
Reviewed-by: Tim Wawrzynczak 
Reviewed-by: Kangheui Won 
---
M src/soc/intel/alderlake/include/soc/pcr_ids.h
1 file changed, 3 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Tim Wawrzynczak: Looks good to me, approved
  Kangheui Won: Looks good to me, approved

diff --git a/src/soc/intel/alderlake/include/soc/pcr_ids.h b/src/soc/intel/alderlake/include/soc/pcr_ids.h
index f125ee2..623a8140 100644
--- a/src/soc/intel/alderlake/include/soc/pcr_ids.h
+++ b/src/soc/intel/alderlake/include/soc/pcr_ids.h
@@ -33,6 +33,9 @@
 #define PID_ITSS	0xc4
 #define PID_SERIALIO	0xcb

+/* eMMC Port ID for Alder Lake N */
+#define PID_EMMC	0xa1
+
 /* CPU Port IDs */
 #define PID_CPU_GPIOCOM0	0xb7
 #define PID_CPU_GPIOCOM1	0xb8