Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68525 )
Change subject: soc/intel: Add node_num to dimm_info struct + adjust dimm_info_fill ......................................................................
soc/intel: Add node_num to dimm_info struct + adjust dimm_info_fill
The dimm_info structure (defined in src/include/memory_info.h) currently does not hold information about the DIMM's node/controller ID.
This patch extends the dimm_info structure by adding a new field for the node ID, called node_num. Also, adapt the dimm_info_fill() function accordingly to populate the newly-added field.
Background: These changes are necessary for the Atlas mainboard, where we are currently experiencing issues with the DIMMs device/bank locator. Our 2 DIMMs share the same CHANNEL and DIMM ID but have a distinct NODE ID. By looking at the smbios table we see Channel-0-DIMM-0 for both DIMMs. Thus, we need their NODE IDs in order to distinguish them.
This patch was tested by building and booting for the Alderlake-P RVP board, which has the same DIMM slot configuration as the Prodrive Atlas mainboard.
Signed-off-by: David Milosevic David.Milosevic@9elements.com Change-Id: I6ffa5bdff0ba0e3c4a4a51f2419291fd1278cd68 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68525 Reviewed-by: Jonathan Zhang jonzhang@fb.com Reviewed-by: Lean Sheng Tan sheng.tan@9elements.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/include/memory_info.h M src/soc/intel/alderlake/romstage/romstage.c M src/soc/intel/apollolake/meminit_util_apl.c M src/soc/intel/apollolake/meminit_util_glk.c M src/soc/intel/cannonlake/romstage/romstage.c M src/soc/intel/common/smbios.c M src/soc/intel/common/smbios.h M src/soc/intel/elkhartlake/romstage/romstage.c M src/soc/intel/icelake/romstage/romstage.c M src/soc/intel/jasperlake/romstage/romstage.c M src/soc/intel/meteorlake/romstage/romstage.c M src/soc/intel/skylake/romstage/romstage.c M src/soc/intel/tigerlake/romstage/romstage.c M src/soc/intel/xeon_sp/cpx/romstage.c 14 files changed, 68 insertions(+), 12 deletions(-)
Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved Jonathan Zhang: Looks good to me, but someone else must approve
diff --git a/src/include/memory_info.h b/src/include/memory_info.h index 676c170..7534a81 100644 --- a/src/include/memory_info.h +++ b/src/include/memory_info.h @@ -33,7 +33,17 @@ */ uint16_t ddr_frequency; uint8_t rank_per_dimm; + /* + * Memory-Controller-ID + */ + uint8_t ctrlr_num; + /* + * Channel-ID + */ uint8_t channel_num; + /* + * DIMM-ID + */ uint8_t dimm_num; uint8_t bank_locator; /* diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index f133910..3ee83bd 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -114,7 +114,8 @@ meminfo_hob->VddVoltage[memProfNum], meminfo_hob->EccSupport, src_dimm->MfgId, - src_dimm->SpdModuleType); + src_dimm->SpdModuleType, + node); index++; } } diff --git a/src/soc/intel/apollolake/meminit_util_apl.c b/src/soc/intel/apollolake/meminit_util_apl.c index 2f025b6..9432011 100644 --- a/src/soc/intel/apollolake/meminit_util_apl.c +++ b/src/soc/intel/apollolake/meminit_util_apl.c @@ -82,6 +82,7 @@ 0, 0, src_dimm->MfgId, + 0, 0); index++; } diff --git a/src/soc/intel/apollolake/meminit_util_glk.c b/src/soc/intel/apollolake/meminit_util_glk.c index baf7862..9922b28 100644 --- a/src/soc/intel/apollolake/meminit_util_glk.c +++ b/src/soc/intel/apollolake/meminit_util_glk.c @@ -88,7 +88,8 @@ 0, 0, src_dimm->MfgId, - src_dimm->SpdModuleType); + src_dimm->SpdModuleType, + node); index++; } } diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index 1ea91da..a417359 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -107,7 +107,8 @@ memory_info_hob->VddVoltage[memProfNum], memory_info_hob->EccSupport, src_dimm->MfgId, - src_dimm->SpdModuleType); + src_dimm->SpdModuleType, + 0); index++; } } diff --git a/src/soc/intel/common/smbios.c b/src/soc/intel/common/smbios.c index bd6de9f..5ab2dbc 100644 --- a/src/soc/intel/common/smbios.c +++ b/src/soc/intel/common/smbios.c @@ -14,7 +14,7 @@ u32 frequency, u8 rank_per_dimm, u8 channel_id, u8 dimm_id, const char *module_part_num, size_t module_part_number_size, const u8 *module_serial_num, u16 data_width, u32 vdd_voltage, - bool ecc_support, u16 mod_id, u8 mod_type) + bool ecc_support, u16 mod_id, u8 mod_type, u8 ctrlr_id) { dimm->mod_id = mod_id; dimm->mod_type = mod_type; @@ -24,6 +24,8 @@ dimm->rank_per_dimm = rank_per_dimm; dimm->channel_num = channel_id; dimm->dimm_num = dimm_id; + dimm->ctrlr_num = ctrlr_id; + if (vdd_voltage > 0xFFFF) { dimm->vdd_voltage = 0xFFFF; } else { diff --git a/src/soc/intel/common/smbios.h b/src/soc/intel/common/smbios.h index 06a35c7..410b2fd 100644 --- a/src/soc/intel/common/smbios.h +++ b/src/soc/intel/common/smbios.h @@ -14,6 +14,6 @@ u32 frequency, u8 rank_per_dimm, u8 channel_id, u8 dimm_id, const char *module_part_num, size_t module_part_number_size, const u8 *module_serial_num, u16 data_width, u32 vdd_voltage, - bool ecc_support, u16 mod_id, u8 mod_type); + bool ecc_support, u16 mod_id, u8 mod_type, u8 ctrlr_id);
#endif /* _COMMON_SMBIOS_H_ */ diff --git a/src/soc/intel/elkhartlake/romstage/romstage.c b/src/soc/intel/elkhartlake/romstage/romstage.c index 39a5a332..427cee5 100644 --- a/src/soc/intel/elkhartlake/romstage/romstage.c +++ b/src/soc/intel/elkhartlake/romstage/romstage.c @@ -112,7 +112,8 @@ meminfo_hob->VddVoltage[memProfNum], meminfo_hob->EccSupport, src_dimm->MfgId, - src_dimm->SpdModuleType); + src_dimm->SpdModuleType, + node); index++; } } diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c index 8575a3f..366ba3fa 100644 --- a/src/soc/intel/icelake/romstage/romstage.c +++ b/src/soc/intel/icelake/romstage/romstage.c @@ -96,7 +96,8 @@ memory_info_hob->VddVoltage[memProfNum], memory_info_hob->EccSupport, src_dimm->MfgId, - src_dimm->SpdModuleType); + src_dimm->SpdModuleType, + 0); index++; } } diff --git a/src/soc/intel/jasperlake/romstage/romstage.c b/src/soc/intel/jasperlake/romstage/romstage.c index 3a2f8b4..9cec859 100644 --- a/src/soc/intel/jasperlake/romstage/romstage.c +++ b/src/soc/intel/jasperlake/romstage/romstage.c @@ -112,7 +112,8 @@ meminfo_hob->VddVoltage[memProfNum], meminfo_hob->EccSupport, src_dimm->MfgId, - src_dimm->SpdModuleType); + src_dimm->SpdModuleType, + node); index++; } } diff --git a/src/soc/intel/meteorlake/romstage/romstage.c b/src/soc/intel/meteorlake/romstage/romstage.c index 2d3b144..bac3caf 100644 --- a/src/soc/intel/meteorlake/romstage/romstage.c +++ b/src/soc/intel/meteorlake/romstage/romstage.c @@ -106,7 +106,8 @@ meminfo_hob->VddVoltage[memProfNum], meminfo_hob->EccSupport, src_dimm->MfgId, - src_dimm->SpdModuleType); + src_dimm->SpdModuleType, + node); index++; } } diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 30401fc..02ae19a 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -111,7 +111,8 @@ memory_info_hob->VddVoltage[memProfNum], memory_info_hob->EccSupport, src_dimm->MfgId, - src_dimm->SpdModuleType); + src_dimm->SpdModuleType, + 0); index++; } } diff --git a/src/soc/intel/tigerlake/romstage/romstage.c b/src/soc/intel/tigerlake/romstage/romstage.c index 3c6e634..c1aca17 100644 --- a/src/soc/intel/tigerlake/romstage/romstage.c +++ b/src/soc/intel/tigerlake/romstage/romstage.c @@ -112,7 +112,8 @@ meminfo_hob->VddVoltage[memProfNum], meminfo_hob->EccSupport, src_dimm->MfgId, - src_dimm->SpdModuleType); + src_dimm->SpdModuleType, + node); index++; } } diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c index 6ce5ef5..c0ecd65 100644 --- a/src/soc/intel/xeon_sp/cpx/romstage.c +++ b/src/soc/intel/xeon_sp/cpx/romstage.c @@ -131,7 +131,8 @@ vdd_voltage, true, /* hard-coded as ECC supported */ src_dimm.VendorID, - src_dimm.actKeyByte2); + src_dimm.actKeyByte2, + 0); index++; } }