John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30918 )
Change subject: soc/intel/apollolake: Override GLK usb clock gating register ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/30918/2/src/soc/intel/apollolake/chip.c File src/soc/intel/apollolake/chip.c:
https://review.coreboot.org/#/c/30918/2/src/soc/intel/apollolake/chip.c@776 PS2, Line 776: reg = 0x0FCE6E5F;
Can you please add those bits as macros here and set them accordingly here? Its difficult to underst […]
#define XHCI_CFG_XHCLKGTEN_MMIO 0x8650 ///< Clock Gating BIT[31:29] Reserved #define NUEFBCGPS BIT28 ///< Naking USB2.0 EPs for Backbone Clock Gating and PLL Shutdown #define SRAMPGTEN BIT27 ///< SRAM Power Gate Enable #define SSLSE BIT26 ///< SS Link PLL Shutdown Enable #define USB2PLLSE BIT25 ///< USB2 PLL Shutdown Enable #define IOSFSTCGE BIT24 ///< IOSF Sideband Trunk Clock Gating Enable #define HSTCGE (BIT23 | BIT22 | BIT21 | BIT20) ///< HS Backbone PXP Trunk Clock Gate Enable #define HSTCGE 20 #define SSTCGE (BIT19 | BIT18 | BIT17 | BIT16) ///< SS Backbone PXP Trunk Clock Gate Enable #define SSTCGE 16 #define XHCIGEU3S BIT15 ///< XHC Ignore_EU3S #define XHCFTCLKSE BIT14 ///< XHC Frame Timer Clock Shutdown Enable #define XHCBBTCGIPISO BIT13 ///< XHC Backbone PXP Trunk Clock Gate In Presence of ISOCH EP #define XHCHSTCGU2NRWE BIT12 ///< XHC HS Backbone PXP Trunk Clock Gate U2 non RWE #define XHCUSB2PLLSDLE (BIT11 | BIT10) ///< XHC USB2 PLL Shutdown Lx Enable #define HSUXDMIPLLSE (BIT9 | BIT8) ///< HS Backbone PXP PLL Shutdown Ux Enable #define HSUXDMIPLLSE 8 #define SSPLLSUE (BIT7 | BIT6 | BIT5) ///< SS backbone PXP PLL Shutdown Ux Enable #define SSPLLSUE 5 #define XHCBLCGE BIT4 ///< XHC Backbone Local Clock Gating Enable #define HSLTCGE BIT3 ///< HS Link Trunk Clock Gating Enable #define SSLTCGE BIT2 ///< SS Link Trunk Clock Gating Enable #define IOSFBTCGE BIT1 ///< IOSF Backbone Trunk Clock Gating Enable #define IOSFGBLCGE BIT0 ///< IOSF Gasket Backbone Local Clock Gating Enable