Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu.
Shuo Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81040?usp=email )
Change subject: soc/intel/xeon_sp: Redefine FSP data types for FSP2.4 ......................................................................
soc/intel/xeon_sp: Redefine FSP data types for FSP2.4
Intel server FSP2.4 introduces UDS_STACK_RES/UDS_SOCKET_RES and retires the usages of STACK_RES/IIO_RESOURCE_INSTANCE. Make redinitions to make Xeon-SP common codes to work for both FSP2.4 before and later.
Change-Id: I28c948525cd6d7ac4b9c3fa67e3c99ec637ed38f Signed-off-by: Shuo Liu shuo.liu@intel.com --- M src/soc/intel/xeon_sp/Makefile.mk M src/soc/intel/xeon_sp/acpi.c M src/soc/intel/xeon_sp/include/soc/chip_common.h A src/soc/intel/xeon_sp/include/soc/fsp_adoption.h D src/soc/intel/xeon_sp/include/soc/fsp_upd.h M src/soc/intel/xeon_sp/include/soc/util.h M src/soc/intel/xeon_sp/uncore_acpi.c 7 files changed, 38 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/81040/1
diff --git a/src/soc/intel/xeon_sp/Makefile.mk b/src/soc/intel/xeon_sp/Makefile.mk index a732c78..a1c8d79 100644 --- a/src/soc/intel/xeon_sp/Makefile.mk +++ b/src/soc/intel/xeon_sp/Makefile.mk @@ -21,6 +21,6 @@ subdirs-$(CONFIG_SOC_INTEL_XEON_RAS) += ras
CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/include -CPPFLAGS_common += -include $(src)/soc/intel/xeon_sp/include/soc/fsp_upd.h +CPPFLAGS_common += -include $(src)/soc/intel/xeon_sp/include/soc/fsp_adoption.h
endif ## XEON_SP_COMMON_BASE diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c index 5eaa762..49a6e8a 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/acpi.c @@ -102,7 +102,7 @@ continue; iio++; for (int stack = 0; stack < MAX_IIO_STACK; ++stack) { - const STACK_RES *ri = + const xSTACK_RES *ri = &hob->PlatformData.IIO_resource[socket].StackRes[stack]; uint32_t ioapic_base = ri->IoApicBase; if (ioapic_base == 0 || ioapic_base == 0xFFFFFFFF) diff --git a/src/soc/intel/xeon_sp/include/soc/chip_common.h b/src/soc/intel/xeon_sp/include/soc/chip_common.h index 847d95a..556e510 100644 --- a/src/soc/intel/xeon_sp/include/soc/chip_common.h +++ b/src/soc/intel/xeon_sp/include/soc/chip_common.h @@ -21,7 +21,7 @@ void iio_pci_domain_scan_bus(struct device *dev); void attach_iio_stacks(struct device *dev);
-void soc_create_ioat_domains(union xeon_domain_path path, struct bus *bus, const STACK_RES *sr); +void soc_create_ioat_domains(union xeon_domain_path path, struct bus *bus, const xSTACK_RES *sr); struct device *dev_find_device_on_socket(uint8_t socket, u16 vendor, u16 device); int iio_pci_domain_socket_from_dev(struct device *dev); int iio_pci_domain_stack_from_dev(struct device *dev); diff --git a/src/soc/intel/xeon_sp/include/soc/fsp_adoption.h b/src/soc/intel/xeon_sp/include/soc/fsp_adoption.h new file mode 100644 index 0000000..90940c5 --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/fsp_adoption.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _FSP_UPD_H_ +#define _FSP_UPD_H_ + +/* + * Intel FSPs of XEON server platforms define FSPX_CONFIG + * instead of FSP_X_CONFIG, which is expected by coreboot. + */ +#define FSP_T_CONFIG FSPT_CONFIG +#define FSP_M_CONFIG FSPM_CONFIG +#define FSP_S_CONFIG FSPS_CONFIG + +/* + * Intel server FSP2.4 introduces UDS_STACK_RES/UDS_SOCKET_RES + * and retires the usages of STACK_RES/IIO_RESOURCE_INSTANCE. + * Make below redinitions to make Xeon-SP common codes to work + * for both FSP2.4 before and later. + */ +#if CONFIG(PLATFORM_USES_FSP2_4) +#define xSTACK_RES UDS_STACK_RES +#define xIIO_RESOURCE_INSTANCE UDS_SOCKET_RES +#else +#define xSTACK_RES STACK_RES +#define xIIO_RESOURCE_INSTANCE IIO_RESOURCE_INSTANCE +#endif + +#endif diff --git a/src/soc/intel/xeon_sp/include/soc/fsp_upd.h b/src/soc/intel/xeon_sp/include/soc/fsp_upd.h deleted file mode 100644 index 15ce96f..0000000 --- a/src/soc/intel/xeon_sp/include/soc/fsp_upd.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#ifndef _FSP_UPD_H_ -#define _FSP_UPD_H_ - -/* - * Intel FSPs of XEON server platforms define FSPX_CONFIG - * instead of FSP_X_CONFIG, which is expected by coreboot. - */ -#define FSP_T_CONFIG FSPT_CONFIG -#define FSP_M_CONFIG FSPM_CONFIG -#define FSP_S_CONFIG FSPS_CONFIG - -#endif diff --git a/src/soc/intel/xeon_sp/include/soc/util.h b/src/soc/intel/xeon_sp/include/soc/util.h index b881cb4..556781b 100644 --- a/src/soc/intel/xeon_sp/include/soc/util.h +++ b/src/soc/intel/xeon_sp/include/soc/util.h @@ -27,13 +27,13 @@
struct iiostack_resource { uint8_t no_of_stacks; - STACK_RES res[CONFIG_MAX_SOCKET * MAX_IIO_STACK]; + xSTACK_RES res[CONFIG_MAX_SOCKET * MAX_IIO_STACK]; };
void get_iiostack_info(struct iiostack_resource *info); -bool is_pcie_iio_stack_res(const STACK_RES *res); -bool is_ubox_stack_res(const STACK_RES *res); -bool is_ioat_iio_stack_res(const STACK_RES *res); +bool is_pcie_iio_stack_res(const xSTACK_RES *res); +bool is_ubox_stack_res(const xSTACK_RES *res); +bool is_ioat_iio_stack_res(const xSTACK_RES *res); void bios_done_msr(void *unused);
#endif diff --git a/src/soc/intel/xeon_sp/uncore_acpi.c b/src/soc/intel/xeon_sp/uncore_acpi.c index b7c6640..3e86097 100644 --- a/src/soc/intel/xeon_sp/uncore_acpi.c +++ b/src/soc/intel/xeon_sp/uncore_acpi.c @@ -252,7 +252,7 @@ int stack, const IIO_UDS *hob) { unsigned long tmp = current; - const STACK_RES *ri = &hob->PlatformData.IIO_resource[socket].StackRes[stack]; + const xSTACK_RES *ri = &hob->PlatformData.IIO_resource[socket].StackRes[stack]; const uint32_t bus = ri->BusBase; const uint32_t pcie_seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment; const uint32_t reg_base = ri->VtdBarAddress; @@ -493,7 +493,7 @@ return current; }
-static unsigned long xeonsp_create_satc_ioat(unsigned long current, const STACK_RES *ri) +static unsigned long xeonsp_create_satc_ioat(unsigned long current, const xSTACK_RES *ri) { for (int b = ri->BusBase; b <= ri->BusLimit; ++b) { struct device *dev = pcidev_path_on_bus(b, PCI_DEVFN(0, 0)); @@ -525,7 +525,7 @@ if (!soc_cpu_is_enabled(socket)) continue; for (int stack = (MAX_LOGIC_IIO_STACK - 1); stack >= 0; --stack) { - const STACK_RES *ri = &hob->PlatformData.IIO_resource[socket].StackRes[stack]; + const xSTACK_RES *ri = &hob->PlatformData.IIO_resource[socket].StackRes[stack]; // Add the IOAT ATS devices to the SATC if (CONFIG(HAVE_IOAT_DOMAINS) && is_ioat_iio_stack_res(ri)) current = xeonsp_create_satc_ioat(current, ri);