[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake/bootblock: Fix FSP CAR

[Patrick Rudolph (Code Review)]

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39491 )

Change subject: soc/intel/cannonlake/bootblock: Fix FSP CAR
......................................................................

soc/intel/cannonlake/bootblock: Fix FSP CAR

Fix FSP CAR on plaforms that have ROM_SIZE of 32MiB.
Tested on Intel CFL, the new code allows to boot using FSP-T.

Change-Id: I4dfee230c3cc883fad0cb92977c8f5570e1a927c
Signed-off-by: Patrick Rudolph 
---
M src/soc/intel/cannonlake/bootblock/bootblock.c
1 file changed, 14 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/39491/1

diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c
index 4cc15fc..861f2ca 100644
--- a/src/soc/intel/cannonlake/bootblock/bootblock.c
+++ b/src/soc/intel/cannonlake/bootblock/bootblock.c
@@ -23,6 +23,18 @@
 #if CONFIG(FSP_CAR)
 #include <FsptUpd.h>

+/*
+ * Limit CodeRegionSize to 16 MiB as the CAR area is placed right below the memory mapped
+ * BIOS region. A ROM size of 32 MiB will cause wrong MTRRs to be set for the CAR area,
+ * which will brick the platform. Assumes that the memory mapped BIOS region is no more
+ * than 16 MiB.
+ */
+#if CONFIG_ROM_SIZE > 16 * 1024 * 1024
+#define CODE_CACHE_SIZE (16 * 1024 * 1024)
+#else
+#define CODE_CACHE_SIZE CONFIG_ROM_SIZE
+#endif
+
 const FSPT_UPD temp_ram_init_params = {
    .FspUpdHeader = {
    	.Signature = 0x545F4450554C4643ULL,	/* 'CFLUPD_T' */
@@ -44,8 +56,8 @@
    	.MicrocodeRegionBase = 0,
    	.MicrocodeRegionSize = 0,
    	.CodeRegionBase =
-			(uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE),
-		.CodeRegionSize = (uint32_t)CONFIG_ROM_SIZE,
+			(uint32_t)(0x100000000ULL - CODE_CACHE_SIZE,
+		.CodeRegionSize = (uint32_t)CODE_CACHE_SIZE,
    },
 };
 #endif