[coreboot-gerrit] Change in coreboot[master]: soc/amd/picasso: Init SPI speeds & mode in psp_verstage

[Matt Papageorge (Code Review)]

Matt Papageorge has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43308 )

Change subject: soc/amd/picasso: Init SPI speeds & mode in psp_verstage
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Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/43308/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/43308/3//COMMIT_MSG@14 
PS3, Line 14: TEST=Build & boot. Verify that boot time decreases & that verstage
> Tested on Morphius, and has no issues. […]

So with my latest EFS patch stack (will push it up soon) I am seeing a substantial improvement in 1st timestamp speed!
With EFS
   0:1st timestamp                                     1,929,066
Without EFS
   0:1st timestamp                                     3,131,943