[coreboot-gerrit] Change in coreboot[master]: mb/google/zork: keep the c-state IO base address alignment

[Aaron Durbin (Code Review)]

Aaron Durbin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44135 )

Change subject: mb/google/zork: keep the c-state IO base address alignment
......................................................................

mb/google/zork: keep the c-state IO base address alignment

Align the C-state MSR value of BSP with AGESA.

BUG=b:162705221
BRANCH=none
TEST=Check the MSR value is correct and BSP can enter CC6 with AVT tool

Signed-off-by: Chris Wang 
Change-Id: Ib98d34af518439d338326446c20601867ad31690
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44135
Tested-by: build bot (Jenkins) 
Reviewed-by: Aaron Durbin 
---
M src/soc/amd/picasso/cpu.c
M src/soc/amd/picasso/include/soc/iomap.h
M src/soc/amd/picasso/southbridge.c
3 files changed, 11 insertions(+), 7 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Aaron Durbin: Looks good to me, approved

diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c
index c42f400..4d6e98d 100644
--- a/src/soc/amd/picasso/cpu.c
+++ b/src/soc/amd/picasso/cpu.c
@@ -46,6 +46,15 @@
    return 1 + (cpuid_ecx(0x80000008) & 0xff);
 }

+static void set_cstate_io_addr(void)
+{
+	msr_t cst_addr;
+
+	cst_addr.hi = 0;
+	cst_addr.lo = ACPI_CPU_CONTROL;
+	wrmsr(MSR_CSTATE_ADDRESS, cst_addr);
+}
+
 static void fill_in_relocation_params(struct smm_relocation_params *params)
 {
    uintptr_t tseg_base;
@@ -109,6 +118,7 @@
 {
    check_mca();
    setup_lapic();
+	set_cstate_io_addr();

amd_update_microcode_from_cbfs();
 }
diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h
index 6b9ad2a..8256836 100644
--- a/src/soc/amd/picasso/include/soc/iomap.h
+++ b/src/soc/amd/picasso/include/soc/iomap.h
@@ -69,7 +69,7 @@
 #define  ACPI_PM1_EN		(ACPI_PM_EVT_BLK + 0x02)	  /* 2 bytes */
 #define  ACPI_PM1_CNT_BLK	(PICASSO_ACPI_IO_BASE + 0x04)     /* 2 bytes */
 #define  ACPI_PM_TMR_BLK	(PICASSO_ACPI_IO_BASE + 0x08)     /* 4 bytes */
-#define  ACPI_CPU_CONTROL	(PICASSO_ACPI_IO_BASE + 0x0c)     /* 6 bytes */
+#define  ACPI_CPU_CONTROL	(PICASSO_ACPI_IO_BASE + 0x13)
 /* doc says 0x14 for GPE0_BLK but FT5 only works with 0x20 */
 #define  ACPI_GPE0_BLK		(PICASSO_ACPI_IO_BASE + 0x20)     /* 8 bytes */
 #define  ACPI_GPE0_STS		(ACPI_GPE0_BLK + 0x00)		  /* 4 bytes */
diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c
index 4cd24dd..54d7640 100644
--- a/src/soc/amd/picasso/southbridge.c
+++ b/src/soc/amd/picasso/southbridge.c
@@ -233,7 +233,6 @@
 static void sb_init_acpi_ports(void)
 {
    u32 reg;
-	msr_t cst_addr;

/* We use some of these ports in SMM regardless of whether or not
     * ACPI tables are generated. Enable these ports indiscriminately.
@@ -244,11 +243,6 @@
    pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK);
    pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK);

-	/* CpuControl is in _SB.CP00, 6 bytes */
-	cst_addr.hi = 0;
-	cst_addr.lo = ACPI_CPU_CONTROL;
-	wrmsr(MSR_CSTATE_ADDRESS, cst_addr);
-
    if (CONFIG(HAVE_SMI_HANDLER)) {
    	/* APMC - SMI Command Port */
    	pm_write16(PM_ACPI_SMI_CMD, APM_CNT);