[coreboot-gerrit] Change in ...coreboot[master]: nb/intel/i945/udelay: Use get_ia32_fsb()

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30799

Change subject: nb/intel/i945/udelay: Use get_ia32_fsb()
......................................................................

nb/intel/i945/udelay: Use get_ia32_fsb()

Change-Id: I2dcc9c9f1646c8d89f45de914eb1a431ef4bef2b
Signed-off-by: Elyes HAOUAS 
---
M src/northbridge/intel/i945/udelay.c
1 file changed, 3 insertions(+), 28 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/30799/1

diff --git a/src/northbridge/intel/i945/udelay.c b/src/northbridge/intel/i945/udelay.c
index 8447453..5f5c1b8 100644
--- a/src/northbridge/intel/i945/udelay.c
+++ b/src/northbridge/intel/i945/udelay.c
@@ -17,8 +17,7 @@
 #include <stdint.h>
 #include <cpu/x86/tsc.h>
 #include <cpu/x86/msr.h>
-#include <cpu/intel/speedstep.h>
-
+#include <cpu/intel/fsb.h>
 /**
  * Intel Core(tm) CPUs always run the TSC at the maximum possible CPU clock
  */
@@ -31,35 +30,11 @@
    u32 fsb = 0, divisor;
    u32 d;			/* ticks per us */

-	msr = rdmsr(MSR_FSB_FREQ);
-	switch (msr.lo & 0x07) {
-	case 5:
-		fsb = 400;
-		break;
-	case 1:
-		fsb = 533;
-		break;
-	case 3:
-		fsb = 667;
-		break;
-	case 2:
-		fsb = 800;
-		break;
-	case 0:
-		fsb = 1067;
-		break;
-	case 4:
-		fsb = 1333;
-		break;
-	case 6:
-		fsb = 1600;
-		break;
-	}
-
+	fsb = get_ia32_fsb();
    msr = rdmsr(IA32_PERF_STATUS);
    divisor = (msr.hi >> 8) & 0x1f;

-	d = (fsb * divisor) / 4;	/* CPU clock is always a quarter. */
+	d = (fsb * divisor);

multiply_to_tsc(&tscd, us, d);