[coreboot-gerrit] Change in coreboot[master]: [RFC] AMD APM_CNT and SMI enablement

[Kyösti Mälkki (Code Review)]

Attention is currently required from: Marshall Dawson, Felix Held.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42563 )

Change subject: [RFC] AMD APM_CNT and SMI enablement
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Patch Set 1:

(2 comments)

File src/soc/amd/picasso/southbridge.c:

https://review.coreboot.org/c/coreboot/+/42563/comment/eddcdfe0_28ad415b 
PS1, Line 238: 	 * ACPI tables are generated. Enable these ports indiscriminately.
> CB:42987

The non-resolving link was probably some follow-up on CB:41971. I am still undecided if I should take my works from 2020 to another repo so there is a bunch of these references to works I forcefully deleted from gerrit.

https://review.coreboot.org/c/coreboot/+/42563/comment/77a3c0be_9f50386e 
PS1, Line 244: 	pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK);
Now that I revisit this, PM1 and GPE0 sound like something chipset_power_state would need to eg. detect previoous sleep state of S3 and wake source. That access would be already (early) in romstage.