Attention is currently required from: Patrick Rudolph. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60227 )
Change subject: [DO NOT SUBMIT] nb/intel/ironlake: Debugging attempts ......................................................................
[DO NOT SUBMIT] nb/intel/ironlake: Debugging attempts
Change-Id: I41e00329e45057ea07c24f3a034fd3bd5575f8cf Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/ironlake/quickpath.c M src/northbridge/intel/ironlake/raminit.c 2 files changed, 93 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/60227/1
diff --git a/src/northbridge/intel/ironlake/quickpath.c b/src/northbridge/intel/ironlake/quickpath.c index 5e04c9c..bca81a1 100644 --- a/src/northbridge/intel/ironlake/quickpath.c +++ b/src/northbridge/intel/ironlake/quickpath.c @@ -191,6 +191,7 @@ delay_f_cycles = div_roundup(2500 - delay_e_over_cycle_ps, 2 * halfcycle_ps(info)); + if (delay_f_cycles > delay_e_cycles) { info->delay46_ps[channel] = delay_e_ps; delay_e_cycles = 0; @@ -239,7 +240,7 @@ (training->reg274265[channel][0] << 16) | training->reg274265[channel][1]); mchbar_write16((channel << 10) + 0x265, - training->reg274265[channel][2] << 8); + training->reg274265[channel][2] << 8); /* read and merging write win */ } if (training->reg2ca9_bit0) mchbar_setbits8(0x2ca9, 1 << 0); diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index bac8832..951e24f 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -309,7 +309,8 @@ slot, rank), 9, 0); - gav(get_580(channel, ((i + 1) << 2) | (rank << 5))); + u16 result = get_580(channel, ((i + 1) << 2) | (rank << 5)); + printk(BIOS_DEBUG, "i = %d, result = 0x%04x\n", i, result); }
toggle_1d0_142_5ff(); @@ -337,6 +338,15 @@ return res; }
+ +static u32 egav_real(int line, u32 in) +{ + printk(BIOS_DEBUG, "%d: EGAV: %x\n", line, in); + return in; +} + +#define egav(x) egav_real(__LINE__, (x)) + static void config_rank(struct raminfo *info, int s3resume, int channel, int slot, int rank) { @@ -351,12 +361,12 @@ else add = 0; if (!s3resume) - gav(rw_test(rank + add)); + egav(rw_test(rank + add)); program_timings(info, 0x00, channel, slot, rank); if (!s3resume) - gav(rw_test(rank + add)); + egav(rw_test(rank + add)); if (!s3resume) - gav(rw_test(rank + add)); + egav(rw_test(rank + add)); write_1d0(0, 0x142, 3, 1); write_1d0(0, 0x103, 6, 1);
@@ -764,12 +774,11 @@ else some_delay_1_cycle_floor--; info->some_delay_1_cycle_floor = some_delay_1_cycle_floor; + const int some_delay_1_ps_ceil = (some_delay_1_cycle_ceil - 1) * cycle_ps(info); if (info->revision_flag_1) some_delay_2_ps = halfcycle_ps(info) >> 6; - some_delay_2_ps += - MAX(some_delay_1_ps - 30, - 2 * halfcycle_ps(info) * (some_delay_1_cycle_ceil - 1) + 1000) + - 375; + + some_delay_2_ps += MAX(some_delay_1_ps - 30, some_delay_1_ps_ceil + 1000) + 375; some_delay_3_ps = halfcycle_ps(info) - some_delay_2_ps % halfcycle_ps(info); info->some_delay_3_halfcycles = 0; @@ -1111,8 +1120,7 @@ high_multiplier = 0; some_delay_ns = 200; some_delay_3_half_cycles = 4; - cas_latency_shift = info->silicon_revision == 0 - || info->silicon_revision == 1 ? 1 : 0; + cas_latency_shift = info->silicon_revision == 0 || info->silicon_revision == 1 ? 1 : 0; if (info->revision < 8) { some_delay_ns = 600; cas_latency_shift = 0; @@ -1449,10 +1457,10 @@ write_1d0(info->cached_training->reg_10b, 0x10b, 6, 1); }
-static void dump_timings(struct raminfo *info) +static void dump_timings_real(struct raminfo *info, int line) { int channel, slot, rank, lane, i; - printk(RAM_SPEW, "Timings:\n"); + printk(RAM_SPEW, "Timings %d:\n", line); FOR_POPULATED_RANKS { printk(RAM_SPEW, "channel %d, slot %d, rank %d\n", channel, slot, rank); @@ -1477,6 +1485,8 @@ info->training.reg_10b); }
+#define dump_timings(x) dump_timings_real(x, __LINE__) + /* Read timings and other registers that need to be restored verbatim and put them to CBMEM. */ @@ -2126,11 +2136,14 @@ } }
+ printk(BIOS_DEBUG, "reg1b3\tresult\n"); + for (reg1b3 = 0; reg1b3 < 0x30 && !validate_state(state); reg1b3++) { u8 failmask = 0; write_1d0(reg1b3 ^ 32, 0x1b3, 6, 1); write_1d0(reg1b3 ^ 32, 0x1a3, 6, 1); failmask = check_testing(info, total_rank, 0); + printk(BIOS_DEBUG, "%d\t0x%02x\n", reg1b3, failmask); mchbar_setbits32(0xfb0, 3 << 16); do_fsm(state, count, failmask, 5, 47, lower_usable, upper_usable, reg1b3); @@ -2613,15 +2626,21 @@ u8 reg178; int count = 0, sum = 0;
+ printk(BIOS_DEBUG, "r178\t 0 1 2 3 4 5 6 7\t 0 1 2 3 4 5 6 7"); + for (reg178 = reg178_min[info->clock_speed_index]; reg178 < reg178_max[info->clock_speed_index]; reg178 += reg178_step[info->clock_speed_index]) { margin[reg178] = -1; + printk(BIOS_DEBUG, "\n%d", reg178); FOR_POPULATED_RANKS_BACKWARDS for (lane = 0; lane < 8; lane++) { int curmargin = timings[reg178][channel][slot][rank][lane].largest - timings[reg178][channel][slot][rank][lane]. smallest + 1; + if (lane == 0) + printk(BIOS_DEBUG, "\t"); + printk(BIOS_DEBUG, "% 4d", curmargin); if (curmargin < margin[reg178]) margin[reg178] = curmargin; } @@ -2632,6 +2651,7 @@ count += weight; } } + printk(BIOS_DEBUG, "\n"); dump_timings(info); if (count == 0) die("Couldn't discover DRAM timings (3)\n"); @@ -3054,6 +3074,65 @@ if (info->revision >= 8) read_4090(info);
+ const u16 lane_timings[4][2][2][2][9] = { + { + { + { + { + 0x15, 0x15, 0x15, 0x14, 0x15, 0x14, 0x15, 0x15, 0x15, + }, + { + 0x16, 0x16, 0x14, 0x13, 0x16, 0x14, 0x15, 0x16, 0x15, + }, + }, + }, + }, + { + { + { + { + 0xe0, 0xe8, 0xc6, 0xf5, 0x73, 0xad, 0x91, 0x9e, 0x100, + }, + { + 0xe0, 0xe8, 0xc0, 0xf1, 0x71, 0xad, 0x91, 0x9f, 0x100, + }, + }, + }, + }, + { + { + { + { + 0xa7, 0xb5, 0x98, 0xd3, 0x50, 0x82, 0x6d, 0x72, 0x97, + }, + { + 0xa6, 0xb6, 0x97, 0xcf, 0x4b, 0x7e, 0x6b, 0x73, 0x97, + }, + }, + }, + }, + { + { + { + { + 0xc1, 0xcc, 0xb3, 0xee, 0x6b, 0x9c, 0x85, 0x8d, 0x97, + }, + { + 0xc0, 0xcd, 0xb2, 0xea, 0x66, 0x98, 0x84, 0x8d, 0x97, + }, + }, + }, + }, + }; + + if (0)memcpy(&info->training.lane_timings, &lane_timings, sizeof(lane_timings)); + + for (int channel = 0; channel < NUM_CHANNELS; channel++) + for (int slot = 0; slot < NUM_SLOTS; slot++) + for (int rank = 0; rank < NUM_RANKS; rank++) + if (info->populated_ranks[channel][slot][rank]) + program_timings(info, 0, channel, slot, rank); + if (!try_cached_training(info)) do_ram_training(info); if ((info->silicon_revision == 2 || info->silicon_revision == 3)