[coreboot-gerrit] Change in coreboot[master]: sb/intel/i82371eb: Do not read PM/SMBus I/O ports at runtime

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41093 )

Change subject: sb/intel/i82371eb: Do not read PM/SMBus I/O ports at runtime
......................................................................

sb/intel/i82371eb: Do not read PM/SMBus I/O ports at runtime

Commit 023fdaffd1 (mb/asus/p2b: Refactor southbridge ACPI stuff)
moved the southbridge ACPI stuff to its own file. It also
(prematurely) listed PM and SMBus I/O port ranges as a #defined
fixed value.

Since these two ranges are not expected to change at runtime anyway,
we can simply drop the ASL code doing the read.

Change-Id: Id5adb37d047621d7c8faf81607ceea4cbcac3d34
Signed-off-by: Keith Hui 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41093
Reviewed-by: Angel Pons 
Tested-by: build bot (Jenkins) 
---
M src/southbridge/intel/i82371eb/acpi/i82371eb.asl
1 file changed, 0 insertions(+), 24 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved

diff --git a/src/southbridge/intel/i82371eb/acpi/i82371eb.asl b/src/southbridge/intel/i82371eb/acpi/i82371eb.asl
index 17fd61d..e3e67ea 100644
--- a/src/southbridge/intel/i82371eb/acpi/i82371eb.asl
+++ b/src/southbridge/intel/i82371eb/acpi/i82371eb.asl
@@ -30,10 +30,6 @@
    	{
    		Name (BUF1, ResourceTemplate ()
    		{
-				/* PM register ports */
-				IO (Decode16, 0x0000, 0x0000, 0x01, 0x40, _Y06)
-				/* SMBus register ports */
-				IO (Decode16, 0x0000, 0x0000, 0x01, 0x10, _Y07)
    			/* PIIX4E ports */
    			/* Aliased DMA ports */
    			IO (Decode16, 0x0010, 0x0010, 0x01, 0x10, )
@@ -51,14 +47,6 @@
    			IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x02, )
    			IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02, )
    		})
-			CreateWordField (BUF1, _Y06._MIN, PMLO)
-			CreateWordField (BUF1, _Y06._MAX, PMRL)
-			CreateWordField (BUF1, _Y07._MIN, SBLO)
-			CreateWordField (BUF1, _Y07._MAX, SBRL)
-			And (_SB.PCI0.PX43.PM00, 0xFFFE, PMLO)
-			And (_SB.PCI0.PX43.SB00, 0xFFFE, SBLO)
-			Store (PMLO, PMRL)
-			Store (SBLO, SBRL)
    		Return (BUF1)
    	}
    }
@@ -145,16 +133,4 @@
    	})
    	Return (BUF1)
    }
-
-	OperationRegion (IPMU, PCI_Config, PMBA, 0x02)
-	Field (IPMU, ByteAcc, NoLock, Preserve)
-	{
-	    PM00,   16
-	}
-
-	OperationRegion (ISMB, PCI_Config, SMBBA, 0x02)
-	Field (ISMB, ByteAcc, NoLock, Preserve)
-	{
-	    SB00,   16
-	}
 }