Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33388 )
Change subject: sb/intel/spi: Check for the SPI lock bit during runtime ......................................................................
Patch Set 1:
(3 comments)
Maybe fetching the SPIBAR could be placed in a separate function.
There seems to be an easier, alternative approach. See inline comments.
https://review.coreboot.org/#/c/33388/1/src/southbridge/intel/common/spi.c File src/southbridge/intel/common/spi.c:
https://review.coreboot.org/#/c/33388/1/src/southbridge/intel/common/spi.c@9... PS1, Line 95: ich9_spi_regs *ich9_spi; Could make it a union with `ich7_spi_regs`.
https://review.coreboot.org/#/c/33388/1/src/southbridge/intel/common/spi.c@3... PS1, Line 353: } With the pointer to the MMIO regs already cached (needs to be added for ICH7, see above), this could be boiled down to:
if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) return !!(read16(&cntlr->ich7_regs->spis) & HSFS_FLOCKDN); else return !!(read16(&cntlr->ich9_regs->hsfs) & HSFS_FLOCKDN);
https://review.coreboot.org/#/c/33388/1/src/southbridge/intel/common/spi.c@4... PS1, Line 427: if (!spi_locked()) { Pass `cntlr` here?