[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/cannonlake: Expose FSP params to be adjusted from devicetre...

[Krzysztof M Sywula (Code Review)]

Hello Thejaswani Putta, Patrick Rudolph, Subrata Banik, Roy Mingi Park, Duncan Laurie, Bora Guvendik, Lijian Zhao, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/32026

to look at the new patch set (#2).

Change subject: soc/intel/cannonlake: Expose FSP params to be adjusted from devicetree.cb
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soc/intel/cannonlake: Expose FSP params to be adjusted from devicetree.cb

PchPmSlpS0VmRuntimeControl, PchPmSlpS0Vm070VSupport, PchPmSlpS0Vm075VSupport: configure voltage margining
SlpS0WithGbeSupport: enable/disable SLP_S0 with GBE support

TEST=Configure params in appropriate devicetree.cb, boot the board with debug FSP and compare if changes are reflected

Change-Id: I02aaf0b77b8fc1555a3a424c02acfada21707d0e
Signed-off-by: Krzysztof Sywula 
---
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/fsp_params.c
2 files changed, 12 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/32026/2