[coreboot-gerrit] Change in coreboot[master]: soc/amd/stoneyridge/romstage.c: Fix AGESA warning

[Richard Spiegel (Code Review)]

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/23785

Change subject: soc/amd/stoneyridge/romstage.c: Fix AGESA warning
......................................................................

soc/amd/stoneyridge/romstage.c: Fix AGESA warning

AmdInitPost returns AGESA_WARNING. This is because AGESA by default
enables bank interleaving, while the HW does not meet the requirements
for it. After some investigation, it was found that AGESA was really
checking rank.

In preparation to control interleaving, create a function that returns
the number of ranks for DDR3 and DDR4.

BUG=b:73118857
TEST= Build and run kahlee. Use a print over serial to display DDR3/DDR4
and the number of ranks. Remove the print before committing.

Change-Id: I002328d1029c968c371ff751986537135231f306
Signed-off-by: Richard Spiegel 
---
M src/soc/amd/stoneyridge/romstage.c
1 file changed, 33 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/23785/1

diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c
index 490fd9e..351a266 100644
--- a/src/soc/amd/stoneyridge/romstage.c
+++ b/src/soc/amd/stoneyridge/romstage.c
@@ -31,6 +31,7 @@
 #include <soc/northbridge.h>
 #include <soc/southbridge.h>
 #include <amdblocks/psp.h>
+#include <amdblocks/dimm_spd.h>

asmlinkage void car_stage_entry(void)
 {
@@ -130,6 +131,36 @@
    post_code(0x50);  /* Should never see this post code. */
 }

+static uint8_t get_total_ranks(const struct soc_amd_stoneyridge_config *cfg)
+{
+	uint8_t err, spd_address, ranks, spd_rank, type, spd[16];
+
+	spd_address = cfg->spd_addr_lookup[0][0][0];
+	err = mainboard_read_spd(spd_address, (void *)spd, 16);
+
+	/* Read the SPD if the mainboard didn't fill the buffer */
+	if (err || (*spd == 0))
+		err = sb_read_spd(spd_address, (void *)spd, 16);
+	if (err)
+		return 1;	/* for safety, just 1 rank */
+
+	type = spd[2];
+	switch (type) {
+	case 0x0b:
+		spd_rank = spd[7];	/* DDR3 */
+		break;
+	case 0x0c:
+		spd_rank = spd[12];	/* DDR4 */
+		break;
+	default:
+		spd_rank = 0;		/* will force 1 rank */
+	}
+	spd_rank &= 0x38;	/* rank mask for DDR3 and DDR4 */
+	ranks = spd_rank >> 3;
+	ranks++;
+	return ranks;
+}
+
 void SetMemParams(AMD_POST_PARAMS *PostParams)
 {
    const struct soc_amd_stoneyridge_config *cfg;
@@ -144,6 +175,8 @@
    }

cfg = dev->chip_info;
+	uint8_t ranks = get_total_ranks(cfg);
+	printk(BIOS_SPEW, "Ranks %d\n", ranks);

PostParams->MemConfig.EnableMemClr = cfg->dram_clear_on_reset;