[coreboot-gerrit] Change in coreboot[master]: soc/intel/jasperlake: Add CdClock frequency config

[Simon Yang (Code Review)]

Attention is currently required from: Nico Huber, Jamie Chen, Subrata Banik, Henry Sun, Tim Wawrzynczak, Paul Menzel, Ren Kuo, Angel Pons, Kane Chen, Patrick Rudolph.
Simon Yang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60009 )

Change subject: soc/intel/jasperlake: Add CdClock frequency config
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Patch Set 18:

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/60009/comment/5d3ebfec_81ada690 
PS17, Line 14:
> When is this setting needed? […]

FSP related behavior already update to issue tracker b/206557434.

File src/soc/intel/jasperlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/60009/comment/3d7571fd_6e78cbeb 
PS17, Line 212: 	params->CdClock = config->cd_clock ? config->cd_clock - 1 : 0xff;
> I wasn't aware of this. […]

Updated fsp header in patchset#18, and the inside of fsp related change will release later.