9 May
2019
9 May
'19
5:33 p.m.
Roy Park has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32456 )
Change subject: mb/google/sarien: Enable LTR for PCIe NVMe root port ......................................................................
Patch Set 2:
It didn't save power for S0iX but it actually saved power ~1Watt for those use cases such as Idle display on, Video playback, Hangout and PLT.
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I9842beda6767f758556747f83cfcedbd00612698
Gerrit-Change-Number: 32456
Gerrit-PatchSet: 2
Gerrit-Owner: Duncan Laurie dlaurie@chromium.org
Gerrit-Reviewer: Duncan Laurie dlaurie@chromium.org
Gerrit-Reviewer: Lijian Zhao lijian.zhao@intel.com
Gerrit-Reviewer: Roy Mingi Park roy.mingi.park@intel.com
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Gerrit-CC: Roy Park roy.mingi.park@intel.corp-partner.google.com
Gerrit-Comment-Date: Thu, 09 May 2019 15:33:14 +0000
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