[coreboot-gerrit] Change in coreboot[master]: mb/intel/cedarisland_crb: Populate 2-socket parameters for FSP-M

[Andrey Petrov (Code Review)]

Andrey Petrov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40917 )

Change subject: mb/intel/cedarisland_crb: Populate 2-socket parameters for FSP-M
......................................................................

mb/intel/cedarisland_crb: Populate 2-socket parameters for FSP-M

These parameters were found to work fine for 2-socket configuration,
for FSP based on tag 16.D.21.

Signed-off-by: Andrey Petrov 
Change-Id: I466a7f2951ef307036ddaed0be0aacf98dd2710f
---
M src/mainboard/intel/cedarisland_crb/romstage.c
1 file changed, 18 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/40917/1

diff --git a/src/mainboard/intel/cedarisland_crb/romstage.c b/src/mainboard/intel/cedarisland_crb/romstage.c
index 94af1b6..b53b2b3 100644
--- a/src/mainboard/intel/cedarisland_crb/romstage.c
+++ b/src/mainboard/intel/cedarisland_crb/romstage.c
@@ -1,8 +1,26 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /* This file is part of the coreboot project. */

+#include <arch/mmio.h>
 #include <soc/romstage.h>

void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
+	FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
+	void *start = (void*) m_cfg;
+
+	// BoardId
+	write8(start + 140, 0x1d);
+
+	// BoardTypeBitmask
+	write32(start + 104, 0x11111111);
+
+	// DebugPrintLevel
+	write8(start + 45, 8);
+
+	// KtiLinkSpeedMode
+	write8(start + 64, 0);
+
+	// KtiPrefetchEn
+	write8(start + 53, 2);
 }