Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58997 )
Change subject: samsung/lumpy,stumpy: Refactor ChromeOS GPIOs ......................................................................
samsung/lumpy,stumpy: Refactor ChromeOS GPIOs
Change-Id: Ic8b189dd82c412aa439694e200d530ae7e71d7e2 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/mainboard/samsung/lumpy/chromeos.c M src/mainboard/samsung/lumpy/onboard.h M src/mainboard/samsung/stumpy/chromeos.c A src/mainboard/samsung/stumpy/onboard.h 4 files changed, 45 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/58997/1
diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index c414fd7..b9e59af 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -9,9 +9,7 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> - -#define GPIO_SPI_WP 24 -#define GPIO_REC_MODE 42 +#include "onboard.h"
#define FLAG_SPI_WP 0 #define FLAG_REC_MODE 1 @@ -42,6 +40,16 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); }
+static bool raw_write_protect_state(void) +{ + return get_gpio(GPIO_SPI_WP); +} + +static bool raw_recovery_mode_switch(void) +{ + return !get_gpio(GPIO_REC_MODE); +} + int get_write_protect_state(void) { const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); @@ -60,10 +68,10 @@ const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
/* Write Protect: GPIO24 = KBC3_SPI_WP#, active high */ - if (get_gpio(GPIO_SPI_WP)) + if (raw_write_protect_state()) flags |= (1 << FLAG_SPI_WP); /* Recovery: GPIO42 = CHP3_REC_MODE#, active low */ - if (!get_gpio(GPIO_REC_MODE)) + if (raw_recovery_mode_switch()) flags |= (1 << FLAG_REC_MODE);
pci_s_write_config32(dev, SATA_SP, flags); diff --git a/src/mainboard/samsung/lumpy/onboard.h b/src/mainboard/samsung/lumpy/onboard.h index d281e2e..d43e1bae 100644 --- a/src/mainboard/samsung/lumpy/onboard.h +++ b/src/mainboard/samsung/lumpy/onboard.h @@ -12,4 +12,10 @@ #define BOARD_TRACKPAD_IRQ 21 #define BOARD_TRACKPAD_WAKE_GPIO 0x1b
+/* Write Protect: GPIO24 = KBC3_SPI_WP#, active high */ +#define GPIO_SPI_WP 24 + +/* Recovery: GPIO42 = CHP3_REC_MODE#, active low */ +#define GPIO_REC_MODE 42 + #endif diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index 489d066..91fabbd 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -8,9 +8,7 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> - -#define GPIO_SPI_WP 68 -#define GPIO_REC_MODE 42 +#include "onboard.h"
#define FLAG_SPI_WP 0 #define FLAG_REC_MODE 1 @@ -38,6 +36,16 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); }
+static bool raw_write_protect_state(void) +{ + return get_gpio(GPIO_SPI_WP); +} + +static bool raw_recovery_mode_switch(void) +{ + return !get_gpio(GPIO_REC_MODE); +} + int get_write_protect_state(void) { const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); @@ -56,10 +64,11 @@ const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
/* Write Protect: GPIO68 = CHP3_SPI_WP, active high */ - if (get_gpio(GPIO_SPI_WP)) + if (raw_write_protect_state()) flags |= (1 << FLAG_SPI_WP); + /* Recovery: GPIO42 = CHP3_REC_MODE#, active low */ - if (!get_gpio(GPIO_REC_MODE)) + if (raw_recovery_mode_switch()) flags |= (1 << FLAG_REC_MODE);
pci_s_write_config32(dev, SATA_SP, flags); diff --git a/src/mainboard/samsung/stumpy/onboard.h b/src/mainboard/samsung/stumpy/onboard.h new file mode 100644 index 0000000..602d456 --- /dev/null +++ b/src/mainboard/samsung/stumpy/onboard.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef STUMPY_ONBOARD_H +#define STUMPY_ONBOARD_H + +/* Recovery: GPIO42 = CHP3_REC_MODE#, active low */ +#define GPIO_REC_MODE 42 + +/* Write Protect: GPIO68 = CHP3_SPI_WP, active high */ +#define GPIO_SPI_WP 68 + +#endif