Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45345 )
Change subject: soc/intel/common/block: Move PRMRR options to CPU subfolder ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/45345/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45345/2//COMMIT_MSG@12 PS2, Line 12: C6DRAM CFL FSP handles that case regardless of which PRMRR size is selected, other FSP might as well.
https://review.coreboot.org/c/coreboot/+/45345/2/src/soc/intel/common/block/... File src/soc/intel/common/block/cpu/Kconfig:
https://review.coreboot.org/c/coreboot/+/45345/2/src/soc/intel/common/block/... PS2, Line 106: prompt "PRMRR size" With FSP doing all the magic for C6DRAM there's no need to show this when SGX isn't supported or disabled.