Marc Jones (marc.jones@se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7250
-gerrit
commit db84323afba5d057f305d0c07b67fbdce2374aaf Author: Vadim Bendebury vbendeb@chromium.org Date: Mon Apr 7 15:26:39 2014 -0700
Provide ability to integrate with QComm SBLs
Ipq8064 SBLs initialize the hardware to prepare it to run an arbitrary user provided bootloader. The only bootloader requirements imposed by the SBLs are that it is concatenated with the SBL chunks in the bootprm AND it uses MBN encapsulation (mostly to specify the size and load address).
This patch adds configuration options to specify the location of the SBL blobs and to require MBN encapsulation of the bootblock.
BRANCH=none BUG=chrome-os-partner:27784
TEST=manual
- the below demonstrates added encapsulation, no code run attempts have been made yet:
$ FEATURES=noclean emerge-storm coreboot $ cd /build/storm/tmp/portage/sys-boot/coreboot-9999/work/coreboot-9999 $ \od -t x4 build/cbfs/fallback/bootblock.bin | head -3 0000000 00000005 00000003 00000000 2a010000 0000020 00000be0 00000be0 2a010be0 00000000 0000040 2a010be0 00000000 e32bf0df e59f0030
Change-Id: Iae30ad08059e2b35c434ac25a410ac2017752957 Signed-off-by: Vadim Bendebury vbendeb@chromium.org Reviewed-on: https://chromium-review.googlesource.com/193511 (cherry picked from commit bf16ea915c723ab124d817e3b0d950282e3cf1c1) Signed-off-by: Marc Jones marc.jones@se-eng.com --- src/soc/qualcomm/ipq806x/Kconfig | 18 ++++++++++++++++++ src/soc/qualcomm/ipq806x/Makefile.inc | 10 ++++++++++ 2 files changed, 28 insertions(+)
diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig index fcf8ccd..0f65990 100644 --- a/src/soc/qualcomm/ipq806x/Kconfig +++ b/src/soc/qualcomm/ipq806x/Kconfig @@ -19,4 +19,22 @@ config CBFS_ROM_OFFSET hex "offset of CBFS data in ROM" default 0x18080
+config MBN_ENCAPSULATION + depends on USE_BLOBS + bool "bootblock encapsulation for ipq8064" + default y + +config SBL_BLOB + depends on USE_BLOBS + string "file name of the Qualcomm SBL blob" + default "3rdparty/cpu/qualcomm/ipq8064/sbls.bin" + help + The path and filename of the binary blob containing + ipq806x early initialization code, as supplied by the + vendor. + +config BOOTBLOCK_BASE + hex "64K bytes left for TZBSP" + default 0x2a010000 + endif diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc index be37581..7c4b48d 100644 --- a/src/soc/qualcomm/ipq806x/Makefile.inc +++ b/src/soc/qualcomm/ipq806x/Makefile.inc @@ -6,3 +6,13 @@ romstage-y += timer.c
ramstage-y += cbfs.c ramstage-y += timer.c + +ifeq ($(CONFIG_MBN_ENCAPSULATION),y) + +$(objcbfs)/%.bin: $(objcbfs)/%.elf + @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" + $(OBJCOPY) -O binary $< $@.prembn + @printf " ADD MBN $(subst $(obj)/,,$(@))\n" + ./util/ipqheader/ipqheader.py $(CONFIG_BOOTBLOCK_BASE) $@.prembn $@.tmp + @mv $@.tmp $@ +endif \ No newline at end of file