Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48659 )
Change subject: [TEST ONLY]hermes: Open LPC MMIO window ......................................................................
[TEST ONLY]hermes: Open LPC MMIO window
Change-Id: I41c34058e954af112aad6eb102efc5c32a0dc7b2 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/mainboard/prodrive/hermes/mainboard.c 1 file changed, 20 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/48659/1
diff --git a/src/mainboard/prodrive/hermes/mainboard.c b/src/mainboard/prodrive/hermes/mainboard.c index b24dd56..b9222a3 100644 --- a/src/mainboard/prodrive/hermes/mainboard.c +++ b/src/mainboard/prodrive/hermes/mainboard.c @@ -1,10 +1,16 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+#include <arch/mmio.h> +#include <console/console.h> +#include <intelblocks/lpc_lib.h> +#include <soc/pci_devs.h> #include <device/device.h> #include "gpio.h"
/* FIXME: Example code below */
+#define LPC_MMIO_RANGE (0xfc800000 - 0x10000) + static void mb_configure_dp1_pwr(bool enable) { gpio_output(GPP_K3, enable); @@ -65,6 +71,15 @@ gpio_output(GPP_G4, enable); }
+static void mainboard_init(struct device *dev) +{ + printk(BIOS_ERR, "BMC MMIO: read32(%x) = %x\n", LPC_MMIO_RANGE, read32((void *)LPC_MMIO_RANGE)); + printk(BIOS_ERR, "BMC MMIO: write32(%x, 0xdeadbeef)\n", LPC_MMIO_RANGE); + write32((void *)LPC_MMIO_RANGE, 0xdeadbeef); + printk(BIOS_ERR, "BMC MMIO: read32(%x) = %x\n", LPC_MMIO_RANGE, read32((void *)LPC_MMIO_RANGE)); + +} + static void mainboard_enable(struct device *dev) { /* FIXME: Do runtime configuration once the board is production ready */ @@ -82,6 +97,11 @@ mb_usb31_fp_pwr_enable(1); mb_usb2_fp1_pwr_enable(1); mb_usb2_fp2_pwr_enable(1); + + dev->ops->init = mainboard_init; + + lpc_open_mmio_window(LPC_MMIO_RANGE, 0x10000); + }
struct chip_operations mainboard_ops = {