Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50289 )
Change subject: soc/amd/cezanne/iomap: move MMIO range comment above MMIO ranges ......................................................................
soc/amd/cezanne/iomap: move MMIO range comment above MMIO ranges
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: Ib7e47e3ba29d171266792fc1ffa8f18e314dc770 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50289 Reviewed-by: Raul Rangel rrangel@chromium.org Reviewed-by: Jason Glenesk jason.glenesk@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/amd/cezanne/include/soc/iomap.h 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Jason Glenesk: Looks good to me, but someone else must approve
diff --git a/src/soc/amd/cezanne/include/soc/iomap.h b/src/soc/amd/cezanne/include/soc/iomap.h index 01b0647..b91ff27 100644 --- a/src/soc/amd/cezanne/include/soc/iomap.h +++ b/src/soc/amd/cezanne/include/soc/iomap.h @@ -3,6 +3,7 @@ #ifndef AMD_CEZANNE_IOMAP_H #define AMD_CEZANNE_IOMAP_H
+/* MMIO Ranges */ /* FCH AL2AHB Registers */ #define ALINK_AHB_ADDRESS 0xfedc0000
@@ -11,7 +12,6 @@ #define APU_UART0_BASE 0xfedc9000 #define APU_UART1_BASE 0xfedca000
-/* MMIO Ranges */ #define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1)
/* I/O Ranges */