[coreboot-gerrit] Change in coreboot[master]: soc/intel/*: Move prmrr_core_configure

[Patrick Rudolph (Code Review)]

Attention is currently required from: Andrey Petrov, Patrick Rudolph.
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49898 )

Change subject: soc/intel/*: Move prmrr_core_configure
......................................................................

soc/intel/*: Move prmrr_core_configure

Move prmrr_core_configure before clearing MCEs.

This is required for the following patch in order to update microcode
after PRMRR has been configured, but before MCEs have been cleared.

According to Document 565432 this should be no issue in regards to
SGX activation.

Change-Id: Id2808a3989adff493aaf4175cbeccd080efaaedf
Signed-off-by: Patrick Rudolph 
---
M src/soc/intel/apollolake/cpu.c
M src/soc/intel/skylake/cpu.c
2 files changed, 8 insertions(+), 8 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/49898/1

diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c
index 65fa4dd..8250be5 100644
--- a/src/soc/intel/apollolake/cpu.c
+++ b/src/soc/intel/apollolake/cpu.c
@@ -49,6 +49,10 @@

void soc_core_init(struct device *cpu)
 {
+	/* Configure Core PRMRR for SGX. */
+	if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE))
+		prmrr_core_configure();
+
    /* Clear out pending MCEs */
    /* TODO(adurbin): Some of these banks are core vs package
    		  scope. For now every CPU clears every bank. */
@@ -67,10 +71,6 @@
    */
    enable_pm_timer_emulation();

-	/* Configure Core PRMRR for SGX. */
-	if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE))
-		prmrr_core_configure();
-
    /* Set Max Non-Turbo ratio if RAPL is disabled. */
    if (CONFIG(APL_SKIP_SET_POWER_LIMITS)) {
    	cpu_set_p_state_to_max_non_turbo_ratio();
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index 6872c12..01be4cb 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -98,6 +98,10 @@
 /* All CPUs including BSP will run the following function. */
 void soc_core_init(struct device *cpu)
 {
+	/* Configure Core PRMRR for SGX. */
+	if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE))
+		prmrr_core_configure();
+
    /* Clear out pending MCEs */
    /* TODO(adurbin): This should only be done on a cold boot. Also, some
     * of these banks are core vs package scope. For now every CPU clears
@@ -127,10 +131,6 @@

/* Enable Turbo */
    enable_turbo();
-
-	/* Configure Core PRMRR for SGX. */
-	if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE))
-		prmrr_core_configure();
 }

static void per_cpu_smm_trigger(void)