[coreboot-gerrit] Change in ...coreboot[master]: TEMP:NOT FOR REVIEW:google/mistral: Implement board reset

[SANTHOSH JANARDHANA HASSAN (Code Review)]

SANTHOSH JANARDHANA HASSAN has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31827

Change subject: TEMP:NOT FOR REVIEW:google/mistral: Implement board reset
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TEMP:NOT FOR REVIEW:google/mistral: Implement board reset

Implement reset using PSHOLD.

Change-Id: I472bf73cc7b227187b284a3730ec5dea5373695c
Signed-off-by: Santhosh Hassan 
---
M src/mainboard/google/mistral/Kconfig
M src/mainboard/google/mistral/Makefile.inc
A src/mainboard/google/mistral/reset.c
M src/soc/qualcomm/qcs405/include/soc/iomap.h
4 files changed, 37 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/31827/1

diff --git a/src/mainboard/google/mistral/Kconfig b/src/mainboard/google/mistral/Kconfig
index eacb9f4..87d2df8 100644
--- a/src/mainboard/google/mistral/Kconfig
+++ b/src/mainboard/google/mistral/Kconfig
@@ -13,7 +13,6 @@
    select SPI_FLASH_GIGADEVICE
    select SPI_FLASH_WINBOND
    select MAINBOARD_HAS_CHROMEOS
-	select MISSING_BOARD_RESET
    select MAINBOARD_HAS_TPM2
    select MAINBOARD_HAS_SPI_TPM_CR50

diff --git a/src/mainboard/google/mistral/Makefile.inc b/src/mainboard/google/mistral/Makefile.inc
index 9eb8246..7f6cb7c 100644
--- a/src/mainboard/google/mistral/Makefile.inc
+++ b/src/mainboard/google/mistral/Makefile.inc
@@ -1,15 +1,19 @@

bootblock-y += memlayout.ld
+bootblock-y += reset.c
 bootblock-y += bootblock.c

verstage-y += memlayout.ld
 verstage-y += chromeos.c
+verstage-y += reset.c
 verstage-y += verstage.c

romstage-y += memlayout.ld
 romstage-y += chromeos.c
+romstage-y += reset.c
 romstage-y += romstage.c

ramstage-y += memlayout.ld
 ramstage-y += chromeos.c
+ramstage-y += reset.c
 ramstage-y += mainboard.c
diff --git a/src/mainboard/google/mistral/reset.c b/src/mainboard/google/mistral/reset.c
new file mode 100644
index 0000000..98fbc0c
--- /dev/null
+++ b/src/mainboard/google/mistral/reset.c
@@ -0,0 +1,31 @@
+/*
+ *
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/iomap.h>
+#include <reset.h>
+
+void do_board_reset(void)
+{
+	/*
+	 * At boot time the boot loaders would have set a magic cookie
+	 * here to detect watchdog reset. However, since this is a
+	 * normal reset clear the magic numbers.
+	 */
+	write32(TCSR_BOOT_MISC_DETECT, 0);
+	write32(TCSR_RESET_DEBUG_SW_ENTRY, 0);
+	write32(GCNT_PSHOLD, 0);
+}
diff --git a/src/soc/qualcomm/qcs405/include/soc/iomap.h b/src/soc/qualcomm/qcs405/include/soc/iomap.h
index 968d6ce..851c607 100644
--- a/src/soc/qualcomm/qcs405/include/soc/iomap.h
+++ b/src/soc/qualcomm/qcs405/include/soc/iomap.h
@@ -36,6 +36,8 @@
 #ifndef __SOC_QUALCOMM_IPQ40XX_IOMAP_H_
 #define __SOC_QUALCOMM_IPQ40XX_IOMAP_H_

+#include <arch/io.h>
+#include <gpio.h>
 #include <device/mmio.h>
 #include <soc/cdp.h>
 #include <soc/blsp.h>