Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42685 )
Change subject: soc/amd/common: Drop ACPIMMIO bank for SMBus device PCI config ......................................................................
Patch Set 8:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42685/8/src/soc/amd/picasso/uart.c File src/soc/amd/picasso/uart.c:
https://review.coreboot.org/c/coreboot/+/42685/8/src/soc/amd/picasso/uart.c@... PS8, Line 106: generator divisor programming? 16*115200 = 1.8432M. */
the register access below switches the clock source for the corresponding UART from 48MHz to 16*1152 […]
See previous comments exchanged with Raul; I could not tell what this does, but assumed it would affect the baudrate divisor registers of UART.
At the time, I just wanted to raise the point the same register write could be done with PCI config register access, so I did not understand the reasoning for using ACPIMMIO here.
Also, with psp-verstage, the first program we have control over, is not capable of doing the write.
https://review.coreboot.org/c/coreboot/+/42685/8/src/soc/amd/picasso/uart.c@... PS8, Line 107: if (CONFIG(AMD_SOC_UART_1_8MZ)) { if (ENV_X86 && CONFIG(AMD_SOC_UART_1_8MZ))