Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36990 )
Change subject: soc/mediatek/mt8183: Tx delay cell should use ddr clock do compute ......................................................................
Patch Set 1: Code-Review+1
(7 comments)
https://review.coreboot.org/c/coreboot/+/36990/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/36990/1//COMMIT_MSG@7 PS1, Line 7: Tx delay cell should use ddr clock do compute Use DDR clock to compute Tx delay cell
https://review.coreboot.org/c/coreboot/+/36990/1//COMMIT_MSG@9 PS1, Line 9: using use
https://review.coreboot.org/c/coreboot/+/36990/1//COMMIT_MSG@9 PS1, Line 9: compute computation
https://review.coreboot.org/c/coreboot/+/36990/1//COMMIT_MSG@9 PS1, Line 9: the The
https://review.coreboot.org/c/coreboot/+/36990/1//COMMIT_MSG@9 PS1, Line 9: ddr clock pll DDR clock PLL
https://review.coreboot.org/c/coreboot/+/36990/1//COMMIT_MSG@10 PS1, Line 10: should not div 2 more. and should not be divided by 2.
https://review.coreboot.org/c/coreboot/+/36990/1/src/soc/mediatek/mt8183/dra... File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/36990/1/src/soc/mediatek/mt8183/dra... PS1, Line 1595: and Bluetooth.