[coreboot-gerrit] Change in coreboot[master]: drivers/intel/fsp1_1: Fake microcode update to make FSP happy

[Arthur Heymans (Code Review)]

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36255 )

Change subject: drivers/intel/fsp1_1: Fake microcode update to make FSP happy
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Patch Set 2:
> Patch Set 2:
>
> Tested how, and how much time is saved?

I suspect very little changes in execution time. Typically microcode for 2-4 stepping is included for these SOC and only the header is check. From coreboot doing the updates + fake microcode for FSP to FSP only, I suspect coreboot being faster as WB-ROM caching is set up to speed up things.