Patrick Georgi (pgeorgi@google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12607
-gerrit
commit 91e85ebd1996f668f4efd2bb62098b39b353df5d Author: CC Ma cc.ma@mediatek.com Date: Fri Jul 31 17:10:58 2015 +0800
google/oak: Add board_id() and ram_code() implementation
BRANCH=none BUG=none TEST=Oak build pass
Change-Id: Ic2fd9b2ec0592d1f7195d72c60dab15961de0a9e Signed-off-by: Patrick Georgi pgeorgi@chromium.org Original-Commit-Id: 4d0b00a779b87b0b625cc2bccd8f7470b79e6410 Original-Change-Id: Id9f17d64e9e30946817b86ec8cdfe67ea3dbc798 Original-Signed-off-by: CC Ma cc.ma@mediatek.com Original-Reviewed-on: https://chromium-review.googlesource.com/292675 Original-Commit-Ready: Yidi Lin yidi.lin@mediatek.com Original-Tested-by: Yidi Lin yidi.lin@mediatek.com Original-Reviewed-by: Julius Werner jwerner@chromium.org --- src/mainboard/google/oak/Kconfig | 1 + src/mainboard/google/oak/Makefile.inc | 3 ++ src/mainboard/google/oak/boardid.c | 60 +++++++++++++++++++++++++++++++++++ src/mainboard/google/oak/gpio.h | 9 ++++++ 4 files changed, 73 insertions(+)
diff --git a/src/mainboard/google/oak/Kconfig b/src/mainboard/google/oak/Kconfig index a7904ca..e45fb4c 100644 --- a/src/mainboard/google/oak/Kconfig +++ b/src/mainboard/google/oak/Kconfig @@ -22,6 +22,7 @@ if BOARD_GOOGLE_OAK config BOARD_SPECIFIC_OPTIONS def_bool y select SOC_MEDIATEK_MT8173 + select BOARD_ID_AUTO select CHROMEOS_VBNV_EC select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_SPI diff --git a/src/mainboard/google/oak/Makefile.inc b/src/mainboard/google/oak/Makefile.inc index dbfc1db..dca67db 100644 --- a/src/mainboard/google/oak/Makefile.inc +++ b/src/mainboard/google/oak/Makefile.inc @@ -20,12 +20,15 @@ bootblock-y += bootblock.c bootblock-y += memlayout.ld bootblock-y += chromeos.c +bootblock-y += boardid.c
romstage-y += chromeos.c romstage-y += romstage.c romstage-y += memlayout.ld +romstage-y += boardid.c
ramstage-y += mainboard.c ramstage-y += chromeos.c ramstage-y += memlayout.ld +ramstage-y += boardid.c
diff --git a/src/mainboard/google/oak/boardid.c b/src/mainboard/google/oak/boardid.c new file mode 100644 index 0000000..fe5ad0a --- /dev/null +++ b/src/mainboard/google/oak/boardid.c @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <boardid.h> +#include <gpio.h> +#include <console/console.h> +#include <stdlib.h> +#include "gpio.h" + +static int board_id_value = -1; + +static uint8_t get_board_id(void) +{ + uint8_t bid = 0; + static gpio_t pins[] = {[2] = BOARD_ID_2, [1] = BOARD_ID_1, + [0] = BOARD_ID_0}; + + bid = gpio_base2_value(pins, ARRAY_SIZE(pins)); + + printk(BIOS_INFO, "Board ID %d\n", bid); + + return bid; +} + +uint8_t board_id(void) +{ + if (board_id_value < 0) + board_id_value = get_board_id(); + + return board_id_value; +} + +uint32_t ram_code(void) +{ + uint32_t code; + static gpio_t pins[] = {[3] = RAM_ID_3, [2] = RAM_ID_2, [1] = RAM_ID_1, + [0] = RAM_ID_0}; + + code = gpio_base2_value(pins, ARRAY_SIZE(pins)); + + printk(BIOS_INFO, "RAM Config: %u\n", code); + + return code; +} diff --git a/src/mainboard/google/oak/gpio.h b/src/mainboard/google/oak/gpio.h index d319749..e07c9e3 100644 --- a/src/mainboard/google/oak/gpio.h +++ b/src/mainboard/google/oak/gpio.h @@ -23,6 +23,15 @@
enum { LID = PAD_EINT12, + /* Board ID related GPIOS. */ + BOARD_ID_0 = PAD_RDN3_A, + BOARD_ID_1 = PAD_RDP3_A, + BOARD_ID_2 = PAD_RDN2_A, + /* RAM ID related GPIOS. */ + RAM_ID_0 = PAD_RDP2_A, + RAM_ID_1 = PAD_RCN_A, + RAM_ID_2 = PAD_RCP_A, + RAM_ID_3 = PAD_RDN1_A, /* Write Protect */ WRITE_PROTECT = PAD_EINT4, /* Power button */