Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50615 )
Change subject: soc/amd: Move update_microcode.c to common/block/cpu ......................................................................
soc/amd: Move update_microcode.c to common/block/cpu
We also want to support uCode loading on cezanne.
Signed-off-by: Raul E Rangel rrangel@chromium.org Change-Id: I6f10564c93ce72aea7ff52a8565d65d8b56452f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50615 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Felix Held felix-coreboot@felixheld.de --- M src/soc/amd/common/block/cpu/Kconfig M src/soc/amd/common/block/cpu/Makefile.inc R src/soc/amd/common/block/cpu/update_microcode.c M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc 5 files changed, 22 insertions(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved
diff --git a/src/soc/amd/common/block/cpu/Kconfig b/src/soc/amd/common/block/cpu/Kconfig index 996605e..f418ee7 100644 --- a/src/soc/amd/common/block/cpu/Kconfig +++ b/src/soc/amd/common/block/cpu/Kconfig @@ -44,3 +44,16 @@ Select this option to add the common functions for getting the TSC frequency of AMD family 17h and 19h CPUs/APUs and to provide TSC- based monotonic timer functionality to the build. + +config SOC_AMD_COMMON_BLOCK_UCODE + bool + select SUPPORT_CPU_UCODE_IN_CBFS + default n + help + Builds in support for loading uCode. + +config SOC_AMD_COMMON_BLOCK_UCODE_SIZE + int + depends on SOC_AMD_COMMON_BLOCK_UCODE + help + Defines the size of the uCode binary in bytes. diff --git a/src/soc/amd/common/block/cpu/Makefile.inc b/src/soc/amd/common/block/cpu/Makefile.inc index 4c02663..f402e70 100644 --- a/src/soc/amd/common/block/cpu/Makefile.inc +++ b/src/soc/amd/common/block/cpu/Makefile.inc @@ -1 +1,2 @@ subdirs-y += ./* +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_UCODE) += update_microcode.c diff --git a/src/soc/amd/picasso/update_microcode.c b/src/soc/amd/common/block/cpu/update_microcode.c similarity index 91% rename from src/soc/amd/picasso/update_microcode.c rename to src/soc/amd/common/block/cpu/update_microcode.c index 47a9835..2ba1802 100644 --- a/src/soc/amd/picasso/update_microcode.c +++ b/src/soc/amd/common/block/cpu/update_microcode.c @@ -8,7 +8,10 @@ #include <cpu/amd/msr.h> #include <cbfs.h>
-#define MPB_MAX_SIZE 3200 +_Static_assert(CONFIG_SOC_AMD_COMMON_BLOCK_UCODE_SIZE > 0, + "SOC_AMD_COMMON_BLOCK_UCODE_SIZE is not set"); + +#define MPB_MAX_SIZE CONFIG_SOC_AMD_COMMON_BLOCK_UCODE_SIZE #define MPB_DATA_OFFSET 32
struct microcode { diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index d037d48..16a1297 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -46,6 +46,7 @@ select SOC_AMD_COMMON_BLOCK_SPI select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H select SOC_AMD_COMMON_BLOCK_UART + select SOC_AMD_COMMON_BLOCK_UCODE select PROVIDES_ROM_SHARING select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select PARALLEL_MP @@ -58,7 +59,9 @@ select FSP_COMPRESS_FSP_S_LZMA select UDK_2017_BINDING select HAVE_CF9_RESET - select SUPPORT_CPU_UCODE_IN_CBFS + +config SOC_AMD_COMMON_BLOCK_UCODE_SIZE + default 3200
config FSP_M_FILE string "FSP-M (memory init) binary path and filename" diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 99e2da1..d2a5e4c 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -48,7 +48,6 @@ ramstage-y += finalize.c ramstage-y += soc_util.c ramstage-y += fsp_params.c -ramstage-y += update_microcode.c ramstage-y += graphics.c ramstage-y += pcie_gpp.c ramstage-y += xhci.c