Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34791 )
Change subject: soc/intel/cannonlake: Speed up postcar loading using intermediate caching ......................................................................
Patch Set 12:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34791/9/src/soc/intel/cannonlake/ro... File src/soc/intel/cannonlake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/34791/9/src/soc/intel/cannonlake/ro... PS9, Line 167: /* Cache the ROM as WP just below 4GiB. */
Yes. And cbmem -t with POSTCAR_STAGE=y for comparison.
localhost ~ # cbmem -t 58 entries total:
0:1st timestamp 12,239 100:start of postcar 307,098 (890) 101:end of postcar 307,099 (0) 99:selfboot jump 647,489 (465)
I am pretty sure this was not with POSTCAR_STAGE=y. Nevertheless, it's now 635ms to enter payload, while it was 650ms before. So I assume this was POSTCAR_STAGE=n with TSEG marked WB cacheable?
if you have trust issue, then i would recommend you to find your HW and identify the data.
Just on trust factor, kindly note if this would have been "POSTCAR_STAGE=n" then cbmem -t entries (which is 58 in all these 3 cases) would have reduced for natural reason. (dropping post car might drop 100 and 101 isn't it ? 100:start of postcar 307,098 (890) 101:end of postcar 307,099 (0))
localhost ~ # cbmem -t 58 entries total:
I am still waiting for cbmem -t from POSTCAR_STAGE=y and TSEG marked WB cacheable. That should be your reference point for the commit message.
As i have told, my last shared data was with POSTCAR_STAGE=y and https://review.coreboot.org/c/coreboot/+/34995 CL.
if you wish to understand the savings then watch below entries in cbmem -t time between last few logs to calculate the direct impact of caching those ranges.
9:finished loading ramstage
Until x86 reset is even de-asserted, the hardware probably already has spent over 150ms for the voltage ramp-ups after you toggled the power button.
These are the pre-reset time, we have means to measure that and optimization those as well.