[coreboot-gerrit] Change in coreboot[master]: drivers/intel/gma: Move IGD OpRegion to CBMEM

[Nico Huber (Code Review)]

Hello Matt DeVillier, Angel Pons, Patrick Rudolph,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/40724

to review the following change.

Change subject: drivers/intel/gma: Move IGD OpRegion to CBMEM
......................................................................

drivers/intel/gma: Move IGD OpRegion to CBMEM

It never was in GNVS, it never belonged among the ACPI tables. Having
it in CBMEM, makes it easy to look the location up on resume, and saves
us additional boilerplate.

Change-Id: I5fdd6634e4a671a85b1df8bc9815296ff42edf29
Signed-off-by: Nico Huber 
---
M src/drivers/intel/gma/opregion.c
M src/drivers/intel/gma/opregion.h
M src/northbridge/intel/gm45/gma.c
M src/northbridge/intel/haswell/gma.c
M src/northbridge/intel/i945/gma.c
M src/northbridge/intel/ironlake/gma.c
M src/northbridge/intel/pineview/gma.c
M src/northbridge/intel/sandybridge/gma.c
M src/northbridge/intel/x4x/gma.c
M src/soc/intel/apollolake/graphics.c
M src/soc/intel/baytrail/acpi/globalnvs.asl
M src/soc/intel/baytrail/gfx.c
M src/soc/intel/baytrail/include/soc/nvs.h
M src/soc/intel/braswell/acpi.c
M src/soc/intel/braswell/acpi/globalnvs.asl
M src/soc/intel/braswell/gfx.c
M src/soc/intel/braswell/include/soc/nvs.h
M src/soc/intel/broadwell/acpi/globalnvs.asl
M src/soc/intel/broadwell/igd.c
M src/soc/intel/broadwell/include/soc/nvs.h
M src/soc/intel/cannonlake/graphics.c
M src/soc/intel/common/block/graphics/graphics.c
M src/soc/intel/common/block/include/intelblocks/graphics.h
M src/soc/intel/icelake/graphics.c
M src/soc/intel/jasperlake/graphics.c
M src/soc/intel/skylake/acpi/globalnvs.asl
M src/soc/intel/skylake/graphics.c
M src/soc/intel/skylake/include/soc/nvs.h
M src/soc/intel/tigerlake/graphics.c
M src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
M src/southbridge/intel/bd82x6x/nvs.h
M src/southbridge/intel/i82801dx/nvs.h
M src/southbridge/intel/i82801gx/acpi/globalnvs.asl
M src/southbridge/intel/i82801gx/nvs.h
M src/southbridge/intel/i82801ix/acpi/globalnvs.asl
M src/southbridge/intel/i82801ix/nvs.h
M src/southbridge/intel/i82801jx/acpi/globalnvs.asl
M src/southbridge/intel/i82801jx/nvs.h
M src/southbridge/intel/ibexpeak/nvs.h
M src/southbridge/intel/lynxpoint/acpi/globalnvs.asl
M src/southbridge/intel/lynxpoint/nvs.h
41 files changed, 82 insertions(+), 1,236 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/40724/1

diff --git a/src/drivers/intel/gma/opregion.c b/src/drivers/intel/gma/opregion.c
index 56449d0..764af46 100644
--- a/src/drivers/intel/gma/opregion.c
+++ b/src/drivers/intel/gma/opregion.c
@@ -69,7 +69,7 @@
 }

/* Write ASLS PCI register and prepare SWSCI register. */
-void intel_gma_opregion_register(uintptr_t opregion)
+static void intel_gma_opregion_register(uintptr_t opregion)
 {
    struct device *igd;
    u16 reg16;
@@ -106,17 +106,16 @@
 }

/* Restore ASLS register on S3 resume and prepare SWSCI. */
-void intel_gma_restore_opregion(void)
+static enum cb_err intel_gma_restore_opregion(void)
 {
-	if (acpi_is_wakeup_s3()) {
-		const void *const gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
-		uintptr_t aslb;
-
-		if (gnvs && (aslb = gma_get_gnvs_aslb(gnvs)))
-			intel_gma_opregion_register(aslb);
-		else
-			printk(BIOS_ERR, "Error: GNVS or ASLB not set.\n");
+	const igd_opregion_t *const opregion = cbmem_find(CBMEM_ID_IGD_OPREGION);
+	if (!opregion) {
+		printk(BIOS_ERR, "GMA: Failed to find IGD OpRegion.\n");
+		return CB_ERR;
    }
+	/* Write ASLS PCI register and prepare SWSCI register. */
+	intel_gma_opregion_register((uintptr_t)opregion);
+	return CB_SUCCESS;
 }

static enum cb_err vbt_validate(struct region_device *rdev)
@@ -236,14 +235,17 @@
 }

/* Initialize IGD OpRegion, called from ACPI code and OS drivers */
-enum cb_err
-intel_gma_init_igd_opregion(igd_opregion_t *opregion)
+enum cb_err intel_gma_init_igd_opregion(void)
 {
+	igd_opregion_t *opregion;
    struct region_device rdev;
    optionrom_vbt_t *vbt = NULL;
    optionrom_vbt_t *ext_vbt;
    bool found = false;

+	if (acpi_is_wakeup_s3())
+		return intel_gma_restore_opregion();
+
    /* Search for vbt.bin in CBFS. */
    if (locate_vbt_cbfs(&rdev) == CB_SUCCESS &&
        vbt_validate(&rdev) == CB_SUCCESS) {
@@ -285,6 +287,12 @@
    	return CB_ERR;
    }

+	opregion = cbmem_add(CBMEM_ID_IGD_OPREGION, sizeof(*opregion));
+	if (!opregion) {
+		printk(BIOS_ERR, "GMA: Failed to add IGD OpRegion to CBMEM.\n");
+		return CB_ERR;
+	}
+
    memset(opregion, 0, sizeof(igd_opregion_t));

memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE,
diff --git a/src/drivers/intel/gma/opregion.h b/src/drivers/intel/gma/opregion.h
index 4967691..69c7bc2 100644
--- a/src/drivers/intel/gma/opregion.h
+++ b/src/drivers/intel/gma/opregion.h
@@ -243,11 +243,7 @@
    u8	coreblock_biossignon[155];
 } __packed optionrom_vbt_t;

-void intel_gma_opregion_register(uintptr_t opregion);
-void intel_gma_restore_opregion(void);
-uintptr_t gma_get_gnvs_aslb(const void *gnvs);
-void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb);
-enum cb_err intel_gma_init_igd_opregion(igd_opregion_t *opregion);
+enum cb_err intel_gma_init_igd_opregion(void);

/*
  * Returns the CBFS filename of the VBT blob.
diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c
index 25f7518..a517622 100644
--- a/src/northbridge/intel/gm45/gma.c
+++ b/src/northbridge/intel/gm45/gma.c
@@ -32,19 +32,6 @@
    write32(res2mmio(gtt_res, reg, 0), data);
 }

-uintptr_t gma_get_gnvs_aslb(const void *gnvs)
-{
-	const global_nvs_t *gnvs_ptr = gnvs;
-	return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0);
-}
-
-void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb)
-{
-	global_nvs_t *gnvs_ptr = gnvs;
-	if (gnvs_ptr)
-		gnvs_ptr->aslb = aslb;
-}
-
 static u32 get_cdclk(struct device *const dev)
 {
    const u16 cdclk_sel =
@@ -205,7 +192,7 @@
    	}
    }

-	intel_gma_restore_opregion();
+	intel_gma_init_igd_opregion();
 }

static void gma_generate_ssdt(struct device *device)
@@ -215,32 +202,6 @@
    drivers_intel_gma_displays_ssdt_generate(&chip->gfx);
 }

-static unsigned long
-gma_write_acpi_tables(struct device *const dev,
-		      unsigned long current,
-		      struct acpi_rsdp *const rsdp)
-{
-	igd_opregion_t *opregion = (igd_opregion_t *)current;
-	global_nvs_t *gnvs;
-
-	if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS)
-		return current;
-
-	current += sizeof(igd_opregion_t);
-
-	/* GNVS has been already set up */
-	gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
-	if (gnvs) {
-		/* IGD OpRegion Base Address */
-		gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion);
-	} else {
-		printk(BIOS_ERR, "Error: GNVS table not found.\n");
-	}
-
-	current = acpi_align_current(current);
-	return current;
-}
-
 static const char *gma_acpi_name(const struct device *dev)
 {
    return "GFX0";
@@ -258,7 +219,6 @@
    .init			= gma_func0_init,
    .ops_pci		= &gma_pci_ops,
    .acpi_name		= gma_acpi_name,
-	.write_acpi_tables	= gma_write_acpi_tables,
 };

static const unsigned short pci_device_ids[] =
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index c6b8fab..f00f8a7 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -210,19 +210,6 @@
    return 0;
 }

-uintptr_t gma_get_gnvs_aslb(const void *gnvs)
-{
-	const global_nvs_t *gnvs_ptr = gnvs;
-	return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0);
-}
-
-void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb)
-{
-	global_nvs_t *gnvs_ptr = gnvs;
-	if (gnvs_ptr)
-		gnvs_ptr->aslb = aslb;
-}
-
 static void power_well_enable(void)
 {
    gtt_write(HSW_PWR_WELL_CTL1, HSW_PWR_WELL_ENABLE);
@@ -510,7 +497,7 @@
    gma_pm_init_post_vbios(dev);

gma_enable_swsci();
-	intel_gma_restore_opregion();
+	intel_gma_init_igd_opregion();
 }

static void gma_generate_ssdt(struct device *dev)
@@ -520,30 +507,6 @@
    drivers_intel_gma_displays_ssdt_generate(&chip->gfx);
 }

-static unsigned long gma_write_acpi_tables(struct device *const dev, unsigned long current,
-					   struct acpi_rsdp *const rsdp)
-{
-	igd_opregion_t *opregion = (igd_opregion_t *)current;
-	global_nvs_t *gnvs;
-
-	if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS)
-		return current;
-
-	current += sizeof(igd_opregion_t);
-
-	/* GNVS has been already set up */
-	gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
-	if (gnvs) {
-		/* IGD OpRegion Base Address */
-		gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion);
-	} else {
-		printk(BIOS_ERR, "Error: GNVS table not found.\n");
-	}
-
-	current = acpi_align_current(current);
-	return current;
-}
-
 static struct pci_operations gma_pci_ops = {
    .set_subsystem = pci_dev_set_subsystem,
 };
@@ -555,7 +518,6 @@
    .init			= gma_func0_init,
    .acpi_fill_ssdt		= gma_generate_ssdt,
    .ops_pci		= &gma_pci_ops,
-	.write_acpi_tables	= gma_write_acpi_tables,
 };

static const unsigned short pci_device_ids[] = {
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index 8a19b3e..794267c 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -44,19 +44,6 @@

#define DEFAULT_BLC_PWM 180

-uintptr_t gma_get_gnvs_aslb(const void *gnvs)
-{
-	const global_nvs_t *gnvs_ptr = gnvs;
-	return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0);
-}
-
-void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb)
-{
-	global_nvs_t *gnvs_ptr = gnvs;
-	if (gnvs_ptr)
-		gnvs_ptr->aslb = aslb;
-}
-
 static int gtt_setup(u8 *mmiobase)
 {
    unsigned long PGETBL_save;
@@ -709,7 +696,7 @@
    	pci_dev_init(dev);
    }

-	intel_gma_restore_opregion();
+	intel_gma_init_igd_opregion();
 }

/* This doesn't reclaim stolen UMA memory, but IGD could still
@@ -764,32 +751,6 @@
    pci_dev_read_resources(dev);
 }

-static unsigned long
-gma_write_acpi_tables(struct device *const dev,
-		      unsigned long current,
-		      struct acpi_rsdp *const rsdp)
-{
-	igd_opregion_t *opregion = (igd_opregion_t *)current;
-	global_nvs_t *gnvs;
-
-	if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS)
-		return current;
-
-	current += sizeof(igd_opregion_t);
-
-	/* GNVS has been already set up */
-	gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
-	if (gnvs) {
-		/* IGD OpRegion Base Address */
-		gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion);
-	} else {
-		printk(BIOS_ERR, "Error: GNVS table not found.\n");
-	}
-
-	current = acpi_align_current(current);
-	return current;
-}
-
 static const char *gma_acpi_name(const struct device *dev)
 {
    return "GFX0";
@@ -808,7 +769,6 @@
    .disable		= gma_func0_disable,
    .ops_pci		= &gma_pci_ops,
    .acpi_name		= gma_acpi_name,
-	.write_acpi_tables	= gma_write_acpi_tables,
 };

diff --git a/src/northbridge/intel/ironlake/gma.c b/src/northbridge/intel/ironlake/gma.c
index c8bbbfd..49068b1 100644
--- a/src/northbridge/intel/ironlake/gma.c
+++ b/src/northbridge/intel/ironlake/gma.c
@@ -65,19 +65,6 @@
    return 0;
 }

-uintptr_t gma_get_gnvs_aslb(const void *gnvs)
-{
-	const global_nvs_t *gnvs_ptr = gnvs;
-	return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0);
-}
-
-void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb)
-{
-	global_nvs_t *gnvs_ptr = gnvs;
-	if (gnvs_ptr)
-		gnvs_ptr->aslb = aslb;
-}
-
 static void gma_pm_init_post_vbios(struct device *dev)
 {
    struct northbridge_intel_ironlake_config *conf = dev->chip_info;
@@ -181,7 +168,7 @@
    gma_pm_init_post_vbios(dev);

gma_enable_swsci();
-	intel_gma_restore_opregion();
+	intel_gma_init_igd_opregion();
 }

static void gma_read_resources(struct device *dev)
@@ -210,32 +197,6 @@
    drivers_intel_gma_displays_ssdt_generate(&chip->gfx);
 }

-static unsigned long
-gma_write_acpi_tables(struct device *const dev,
-		      unsigned long current,
-		      struct acpi_rsdp *const rsdp)
-{
-	igd_opregion_t *opregion = (igd_opregion_t *)current;
-	global_nvs_t *gnvs;
-
-	if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS)
-		return current;
-
-	current += sizeof(igd_opregion_t);
-
-	/* GNVS has been already set up */
-	gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
-	if (gnvs) {
-		/* IGD OpRegion Base Address */
-		gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion);
-	} else {
-		printk(BIOS_ERR, "Error: GNVS table not found.\n");
-	}
-
-	current = acpi_align_current(current);
-	return current;
-}
-
 static struct pci_operations gma_pci_ops = {
    .set_subsystem = pci_dev_set_subsystem,
 };
@@ -247,7 +208,6 @@
    .acpi_fill_ssdt		= gma_generate_ssdt,
    .init			= gma_func0_init,
    .ops_pci		= &gma_pci_ops,
-	.write_acpi_tables	= gma_write_acpi_tables,
 };

static const unsigned short pci_device_ids[] = {
diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c
index d398b55..0d4e34d 100644
--- a/src/northbridge/intel/pineview/gma.c
+++ b/src/northbridge/intel/pineview/gma.c
@@ -43,19 +43,6 @@
 static struct resource *gtt_res  = NULL;
 static struct resource *mmio_res = NULL;

-uintptr_t gma_get_gnvs_aslb(const void *gnvs)
-{
-	const global_nvs_t *gnvs_ptr = gnvs;
-	return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0);
-}
-
-void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb)
-{
-	global_nvs_t *gnvs_ptr = gnvs;
-	if (gnvs_ptr)
-		gnvs_ptr->aslb = aslb;
-}
-
 static int gtt_setup(u8 *mmiobase)
 {
    u32 gttbase;
@@ -275,31 +262,7 @@
    	generate_fake_intel_oprom(&conf->gfx, dev, "$VBT PINEVIEW");
    }

-	intel_gma_restore_opregion();
-}
-
-static unsigned long gma_write_acpi_tables(struct device *const dev, unsigned long current,
-					   struct acpi_rsdp *const rsdp)
-{
-	igd_opregion_t *opregion = (igd_opregion_t *)current;
-	global_nvs_t *gnvs;
-
-	if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS)
-		return current;
-
-	current += sizeof(igd_opregion_t);
-
-	/* GNVS has been already set up */
-	gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
-	if (gnvs) {
-		/* IGD OpRegion Base Address */
-		gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion);
-	} else {
-		printk(BIOS_ERR, "Error: GNVS table not found.\n");
-	}
-
-	current = acpi_align_current(current);
-	return current;
+	intel_gma_init_igd_opregion();
 }

static const char *gma_acpi_name(const struct device *dev)
@@ -318,7 +281,6 @@
    .init                   = gma_func0_init,
    .ops_pci                = &gma_pci_ops,
    .acpi_name              = gma_acpi_name,
-	.write_acpi_tables      = gma_write_acpi_tables,
 };

static const unsigned short pci_device_ids[] =
diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c
index 5c4f548..7a7a767 100644
--- a/src/northbridge/intel/sandybridge/gma.c
+++ b/src/northbridge/intel/sandybridge/gma.c
@@ -303,19 +303,6 @@
    return 0;
 }

-uintptr_t gma_get_gnvs_aslb(const void *gnvs)
-{
-	const global_nvs_t *gnvs_ptr = gnvs;
-	return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0);
-}
-
-void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb)
-{
-	global_nvs_t *gnvs_ptr = gnvs;
-	if (gnvs_ptr)
-		gnvs_ptr->aslb = aslb;
-}
-
 static void gma_pm_init_pre_vbios(struct device *dev)
 {
    u32 reg32;
@@ -637,7 +624,7 @@
    }

gma_enable_swsci();
-	intel_gma_restore_opregion();
+	intel_gma_init_igd_opregion();
 }

static void gma_generate_ssdt(struct device *device)
@@ -647,30 +634,6 @@
    drivers_intel_gma_displays_ssdt_generate(&chip->gfx);
 }

-static unsigned long gma_write_acpi_tables(struct device *const dev, unsigned long current,
-					   struct acpi_rsdp *const rsdp)
-{
-	igd_opregion_t *opregion = (igd_opregion_t *)current;
-	global_nvs_t *gnvs;
-
-	if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS)
-		return current;
-
-	current += sizeof(igd_opregion_t);
-
-	/* GNVS has been already set up */
-	gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
-	if (gnvs) {
-		/* IGD OpRegion Base Address */
-		gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion);
-	} else {
-		printk(BIOS_ERR, "Error: GNVS table not found.\n");
-	}
-
-	current = acpi_align_current(current);
-	return current;
-}
-
 static const char *gma_acpi_name(const struct device *dev)
 {
    return "GFX0";
@@ -702,7 +665,6 @@
    .disable                = gma_func0_disable,
    .ops_pci                = &gma_pci_ops,
    .acpi_name              = gma_acpi_name,
-	.write_acpi_tables      = gma_write_acpi_tables,
 };

static const unsigned short pci_device_ids[] = {
diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c
index f5335ec..133008a 100644
--- a/src/northbridge/intel/x4x/gma.c
+++ b/src/northbridge/intel/x4x/gma.c
@@ -28,19 +28,6 @@

#define BASE_FREQUENCY 96000

-uintptr_t gma_get_gnvs_aslb(const void *gnvs)
-{
-	const global_nvs_t *gnvs_ptr = gnvs;
-	return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0);
-}
-
-void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb)
-{
-	global_nvs_t *gnvs_ptr = gnvs;
-	if (gnvs_ptr)
-		gnvs_ptr->aslb = aslb;
-}
-
 static void gma_func0_init(struct device *dev)
 {
    u32 reg32;
@@ -67,7 +54,7 @@
    	pci_dev_init(dev);
    }

-	intel_gma_restore_opregion();
+	intel_gma_init_igd_opregion();
 }

static void gma_func0_disable(struct device *dev)
@@ -87,32 +74,6 @@
    drivers_intel_gma_displays_ssdt_generate(&chip->gfx);
 }

-static unsigned long
-gma_write_acpi_tables(struct device *const dev,
-		      unsigned long current,
-		      struct acpi_rsdp *const rsdp)
-{
-	igd_opregion_t *opregion = (igd_opregion_t *)current;
-	global_nvs_t *gnvs;
-
-	if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS)
-		return current;
-
-	current += sizeof(igd_opregion_t);
-
-	/* GNVS has been already set up */
-	gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
-	if (gnvs) {
-		/* IGD OpRegion Base Address */
-		gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion);
-	} else {
-		printk(BIOS_ERR, "Error: GNVS table not found.\n");
-	}
-
-	current = acpi_align_current(current);
-	return current;
-}
-
 static const char *gma_acpi_name(const struct device *dev)
 {
    return "GFX0";
@@ -131,7 +92,6 @@
    .ops_pci		= &gma_pci_ops,
    .disable		= gma_func0_disable,
    .acpi_name		= gma_acpi_name,
-	.write_acpi_tables	= gma_write_acpi_tables,
 };

static const unsigned short pci_device_ids[] = {
diff --git a/src/soc/intel/apollolake/graphics.c b/src/soc/intel/apollolake/graphics.c
index 033b300..36e0a26 100644
--- a/src/soc/intel/apollolake/graphics.c
+++ b/src/soc/intel/apollolake/graphics.c
@@ -50,21 +50,6 @@
    	/* Initialize PCI device, load/execute BIOS Option ROM */
    	pci_dev_init(dev);
    }
-}

-uintptr_t graphics_soc_write_acpi_opregion(struct device *device,
-		uintptr_t current, struct acpi_rsdp *rsdp)
-{
-	igd_opregion_t *opregion;
-
-	printk(BIOS_DEBUG, "ACPI:    * IGD OpRegion\n");
-	opregion = (igd_opregion_t *)current;
-
-	if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS)
-		return current;
-
-	/* FIXME: Add platform specific mailbox initialization */
-
-	current += sizeof(igd_opregion_t);
-	return acpi_align_current(current);
+	intel_gma_init_igd_opregion();
 }
diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl
index 4aa600f..83d7f46 100644
--- a/src/soc/intel/baytrail/acpi/globalnvs.asl
+++ b/src/soc/intel/baytrail/acpi/globalnvs.asl
@@ -54,48 +54,6 @@
    TOLM,	 32,	// 0x34 - Top of Low Memory
    CBMC,	 32,	// 0x38 - coreboot mem console pointer

-	/* IGD OpRegion */
-	Offset (0xb4),
-	ASLB,	32,	// 0xb4 - IGD OpRegion Base Address
-	IBTT,	 8,	// 0xb8 - IGD boot panel device
-	IPAT,	 8,	// 0xb9 - IGD panel type CMOS option
-	ITVF,	 8,	// 0xba - IGD TV format CMOS option
-	ITVM,	 8,	// 0xbb - IGD TV minor format option
-	IPSC,	 8,	// 0xbc - IGD panel scaling
-	IBLC,	 8,	// 0xbd - IGD BLC config
-	IBIA,	 8,	// 0xbe - IGD BIA config
-	ISSC,	 8,	// 0xbf - IGD SSC config
-	I409,	 8,	// 0xc0 - IGD 0409 modified settings
-	I509,	 8,	// 0xc1 - IGD 0509 modified settings
-	I609,	 8,	// 0xc2 - IGD 0609 modified settings
-	I709,	 8,	// 0xc3 - IGD 0709 modified settings
-	IDMM,	 8,	// 0xc4 - IGD Power conservation feature
-	IDMS,	 8,	// 0xc5 - IGD DVMT memory size
-	IF1E,	 8,	// 0xc6 - IGD function 1 enable
-	HVCO,	 8,	// 0xc7 - IGD HPLL VCO
-	NXD1,	32,	// 0xc8 - IGD _DGS next DID1
-	NXD2,	32,	// 0xcc - IGD _DGS next DID2
-	NXD3,	32,	// 0xd0 - IGD _DGS next DID3
-	NXD4,	32,	// 0xd4 - IGD _DGS next DID4
-	NXD5,	32,	// 0xd8 - IGD _DGS next DID5
-	NXD6,	32,	// 0xdc - IGD _DGS next DID6
-	NXD7,	32,	// 0xe0 - IGD _DGS next DID7
-	NXD8,	32,	// 0xe4 - IGD _DGS next DID8
-
-	ISCI,	 8,	// 0xe8 - IGD SMI/SCI mode (0: SCI)
-	PAVP,	 8,	// 0xe9 - IGD PAVP data
-	Offset (0xeb),
-	OSCC,	 8,	// 0xeb - PCIe OSC control
-	NPCE,	 8,	// 0xec - native PCIe support
-	PLFL,	 8,	// 0xed - platform flavor
-	BREV,	 8,	// 0xee - board revision
-	DPBM,	 8,	// 0xef - digital port b mode
-	DPCM,	 8,	// 0xf0 - digital port c mode
-	DPDM,	 8,	// 0xf1 - digital port d mode
-	ALFP,	 8,	// 0xf2 - active lfp
-	IMON,	 8,	// 0xf3 - current graphics turbo imon value
-	MMIO,	 8,	// 0xf4 - 64bit mmio support
-
    /* ChromeOS specific */
    Offset (0x100),
    #include <vendorcode/google/chromeos/acpi/gnvs.asl>
diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c
index 64c9061..9b9679f 100644
--- a/src/soc/intel/baytrail/gfx.c
+++ b/src/soc/intel/baytrail/gfx.c
@@ -353,19 +353,6 @@
    }
 }

-uintptr_t gma_get_gnvs_aslb(const void *gnvs)
-{
-	const global_nvs_t *gnvs_ptr = gnvs;
-	return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0);
-}
-
-void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb)
-{
-	global_nvs_t *gnvs_ptr = gnvs;
-	if (gnvs_ptr)
-		gnvs_ptr->aslb = aslb;
-}
-
 static void gfx_init(struct device *dev)
 {
    /* Pre VBIOS Init */
@@ -382,8 +369,7 @@
    /* Post VBIOS Init */
    gfx_post_vbios_init(dev);

-	/* Restore opregion on S3 resume */
-	intel_gma_restore_opregion();
+	intel_gma_init_igd_opregion();
 }

static void gma_generate_ssdt(struct device *dev)
@@ -393,39 +379,12 @@
    drivers_intel_gma_displays_ssdt_generate(&chip->gfx);
 }

-static unsigned long
-gma_write_acpi_tables(struct device *const dev,
-		      unsigned long current,
-		      struct acpi_rsdp *const rsdp)
-{
-	igd_opregion_t *opregion = (igd_opregion_t *)current;
-	global_nvs_t *gnvs;
-
-	if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS)
-		return current;
-
-	current += sizeof(igd_opregion_t);
-
-	/* GNVS has been already set up */
-	gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
-	if (gnvs) {
-		/* IGD OpRegion Base Address */
-		gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion);
-	} else {
-		printk(BIOS_ERR, "Error: GNVS table not found.\n");
-	}
-
-	current = acpi_align_current(current);
-	return current;
-}
-
 static struct device_operations gfx_device_ops = {
    .read_resources		= pci_dev_read_resources,
    .set_resources		= pci_dev_set_resources,
    .enable_resources	= pci_dev_enable_resources,
    .init			= gfx_init,
    .ops_pci		= &soc_pci_ops,
-	.write_acpi_tables	= gma_write_acpi_tables,
    .acpi_fill_ssdt		= gma_generate_ssdt,
 };

diff --git a/src/soc/intel/baytrail/include/soc/nvs.h b/src/soc/intel/baytrail/include/soc/nvs.h
index df81573..e7c64b9 100644
--- a/src/soc/intel/baytrail/include/soc/nvs.h
+++ b/src/soc/intel/baytrail/include/soc/nvs.h
@@ -47,40 +47,7 @@
    u32	cbmc; /* 0x38 - coreboot memconsole */
    u8	rsvd3[120]; /* 0x3c - 0xb3 - unused */

-	/* IGD OpRegion */
-	u32	aslb; /* 0xb4 - IGD OpRegion Base Address */
-	u8	ibtt; /* 0xb8 - IGD boot type */
-	u8	ipat; /* 0xb9 - IGD panel type */
-	u8	itvf; /* 0xba - IGD TV format */
-	u8	itvm; /* 0xbb - IGD TV minor format */
-	u8	ipsc; /* 0xbc - IGD Panel Scaling */
-	u8	iblc; /* 0xbd - IGD BLC configuration */
-	u8	ibia; /* 0xbe - IGD BIA configuration */
-	u8	issc; /* 0xbf - IGD SSC configuration */
-	u8	i409; /* 0xc0 - IGD 0409 modified settings */
-	u8	i509; /* 0xc1 - IGD 0509 modified settings */
-	u8	i609; /* 0xc2 - IGD 0609 modified settings */
-	u8	i709; /* 0xc3 - IGD 0709 modified settings */
-	u8	idmm; /* 0xc4 - IGD Power Conservation */
-	u8	idms; /* 0xc5 - IGD DVMT memory size */
-	u8	if1e; /* 0xc6 - IGD Function 1 Enable */
-	u8	hvco; /* 0xc7 - IGD HPLL VCO */
-	u32	nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */
-	u8	isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */
-	u8	pavp; /* 0xe9 - IGD PAVP data */
-	u8	rsvd12; /* 0xea - rsvd */
-	u8	oscc; /* 0xeb - PCIe OSC control */
-	u8	npce; /* 0xec - native PCIe support */
-	u8	plfl; /* 0xed - platform flavor */
-	u8	brev; /* 0xee - board revision */
-	u8	dpbm; /* 0xef - digital port b mode */
-	u8	dpcm; /* 0xf0 - digital port c mode */
-	u8	dpdm; /* 0xf1 - digital port c mode */
-	u8	alfp; /* 0xf2 - active lfp */
-	u8	imon; /* 0xf3 - current graphics turbo imon value */
-	u8	mmio; /* 0xf4 - 64bit mmio support */
-
-	u8	unused[11];
+	u8	unused[76];

/* ChromeOS specific (0x100-0xfff)*/
    chromeos_acpi_t chromeos;
diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c
index 1e6cea2..2bcc873 100644
--- a/src/soc/intel/braswell/acpi.c
+++ b/src/soc/intel/braswell/acpi.c
@@ -461,14 +461,6 @@
    return current;
 }

-/* Initialize IGD OpRegion, called from ACPI code */
-static int update_igd_opregion(igd_opregion_t *opregion)
-{
-	/* FIXME: Add platform specific mailbox initialization */
-
-	return 0;
-}
-
 unsigned long southcluster_write_acpi_tables(struct device *device, unsigned long current,
    				     struct acpi_rsdp *rsdp)
 {
@@ -480,19 +472,6 @@
    	current = acpi_align_current(current);
    }

-	if (CONFIG(INTEL_GMA_ADD_VBT)) {
-		igd_opregion_t *opregion;
-
-		printk(BIOS_DEBUG, "ACPI:    * IGD OpRegion\n");
-		opregion = (igd_opregion_t *)current;
-		intel_gma_init_igd_opregion(opregion);
-		if (gnvs)
-			gnvs->aslb = (u32)opregion;
-		update_igd_opregion(opregion);
-		current += sizeof(igd_opregion_t);
-		current = acpi_align_current(current);
-	}
-
    ssdt2 = (acpi_header_t *)current;
    memset(ssdt2, 0, sizeof(acpi_header_t));
    acpi_create_serialio_ssdt(ssdt2);
diff --git a/src/soc/intel/braswell/acpi/globalnvs.asl b/src/soc/intel/braswell/acpi/globalnvs.asl
index 860f4d7..4f6ed90 100644
--- a/src/soc/intel/braswell/acpi/globalnvs.asl
+++ b/src/soc/intel/braswell/acpi/globalnvs.asl
@@ -56,48 +56,6 @@
    TOLM,	 32,	/* 0x34 - Top of Low Memory */
    CBMC,	 32,	/* 0x38 - coreboot mem console pointer */

-	/* IGD OpRegion */
-	Offset (0xb4),
-	ASLB,	32,	// 0xb4 - IGD OpRegion Base Address
-	IBTT,	 8,	// 0xb8 - IGD boot panel device
-	IPAT,	 8,	// 0xb9 - IGD panel type CMOS option
-	ITVF,	 8,	// 0xba - IGD TV format CMOS option
-	ITVM,	 8,	// 0xbb - IGD TV minor format option
-	IPSC,	 8,	// 0xbc - IGD panel scaling
-	IBLC,	 8,	// 0xbd - IGD BLC config
-	IBIA,	 8,	// 0xbe - IGD BIA config
-	ISSC,	 8,	// 0xbf - IGD SSC config
-	I409,	 8,	// 0xc0 - IGD 0409 modified settings
-	I509,	 8,	// 0xc1 - IGD 0509 modified settings
-	I609,	 8,	// 0xc2 - IGD 0609 modified settings
-	I709,	 8,	// 0xc3 - IGD 0709 modified settings
-	IDMM,	 8,	// 0xc4 - IGD Power conservation feature
-	IDMS,	 8,	// 0xc5 - IGD DVMT memory size
-	IF1E,	 8,	// 0xc6 - IGD function 1 enable
-	HVCO,	 8,	// 0xc7 - IGD HPLL VCO
-	NXD1,	32,	// 0xc8 - IGD _DGS next DID1
-	NXD2,	32,	// 0xcc - IGD _DGS next DID2
-	NXD3,	32,	// 0xd0 - IGD _DGS next DID3
-	NXD4,	32,	// 0xd4 - IGD _DGS next DID4
-	NXD5,	32,	// 0xd8 - IGD _DGS next DID5
-	NXD6,	32,	// 0xdc - IGD _DGS next DID6
-	NXD7,	32,	// 0xe0 - IGD _DGS next DID7
-	NXD8,	32,	// 0xe4 - IGD _DGS next DID8
-
-	ISCI,	 8,	// 0xe8 - IGD SMI/SCI mode (0: SCI)
-	PAVP,	 8,	// 0xe9 - IGD PAVP data
-	Offset (0xeb),
-	OSCC,	 8,	// 0xeb - PCIe OSC control
-	NPCE,	 8,	// 0xec - native PCIe support
-	PLFL,	 8,	// 0xed - platform flavor
-	BREV,	 8,	// 0xee - board revision
-	DPBM,	 8,	// 0xef - digital port b mode
-	DPCM,	 8,	// 0xf0 - digital port c mode
-	DPDM,	 8,	// 0xf1 - digital port d mode
-	ALFP,	 8,	// 0xf2 - active lfp
-	IMON,	 8,	// 0xf3 - current graphics turbo imon value
-	MMIO,	 8,	// 0xf4 - 64bit mmio support
-
    /* ChromeOS specific */
    Offset (0x100),
    #include <vendorcode/google/chromeos/acpi/gnvs.asl>
diff --git a/src/soc/intel/braswell/gfx.c b/src/soc/intel/braswell/gfx.c
index d6671f6..a603268 100644
--- a/src/soc/intel/braswell/gfx.c
+++ b/src/soc/intel/braswell/gfx.c
@@ -61,20 +61,7 @@
    	/* Post VBIOS Init */
    	gfx_post_vbios_init(dev);
    }
-	intel_gma_restore_opregion();
-}
-
-uintptr_t gma_get_gnvs_aslb(const void *gnvs)
-{
-	const global_nvs_t *gnvs_ptr = gnvs;
-	return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0);
-}
-
-void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb)
-{
-	global_nvs_t *gnvs_ptr = gnvs;
-	if (gnvs_ptr)
-		gnvs_ptr->aslb = aslb;
+	intel_gma_init_igd_opregion();
 }

static void gma_generate_ssdt(struct device *dev)
diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h
index 32d6b8a..adefcda 100644
--- a/src/soc/intel/braswell/include/soc/nvs.h
+++ b/src/soc/intel/braswell/include/soc/nvs.h
@@ -49,40 +49,7 @@
    u32	cbmc; /* 0x38 - coreboot memconsole */
    u8	rsvd3[120]; /* 0x3c - 0xb3 - unused */

-	/* IGD OpRegion */
-	u32	aslb; /* 0xb4 - IGD OpRegion Base Address */
-	u8	ibtt; /* 0xb8 - IGD boot type */
-	u8	ipat; /* 0xb9 - IGD panel type */
-	u8	itvf; /* 0xba - IGD TV format */
-	u8	itvm; /* 0xbb - IGD TV minor format */
-	u8	ipsc; /* 0xbc - IGD Panel Scaling */
-	u8	iblc; /* 0xbd - IGD BLC configuration */
-	u8	ibia; /* 0xbe - IGD BIA configuration */
-	u8	issc; /* 0xbf - IGD SSC configuration */
-	u8	i409; /* 0xc0 - IGD 0409 modified settings */
-	u8	i509; /* 0xc1 - IGD 0509 modified settings */
-	u8	i609; /* 0xc2 - IGD 0609 modified settings */
-	u8	i709; /* 0xc3 - IGD 0709 modified settings */
-	u8	idmm; /* 0xc4 - IGD Power Conservation */
-	u8	idms; /* 0xc5 - IGD DVMT memory size */
-	u8	if1e; /* 0xc6 - IGD Function 1 Enable */
-	u8	hvco; /* 0xc7 - IGD HPLL VCO */
-	u32	nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */
-	u8	isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */
-	u8	pavp; /* 0xe9 - IGD PAVP data */
-	u8	rsvd12; /* 0xea - rsvd */
-	u8	oscc; /* 0xeb - PCIe OSC control */
-	u8	npce; /* 0xec - native PCIe support */
-	u8	plfl; /* 0xed - platform flavor */
-	u8	brev; /* 0xee - board revision */
-	u8	dpbm; /* 0xef - digital port b mode */
-	u8	dpcm; /* 0xf0 - digital port c mode */
-	u8	dpdm; /* 0xf1 - digital port c mode */
-	u8	alfp; /* 0xf2 - active lfp */
-	u8	imon; /* 0xf3 - current graphics turbo imon value */
-	u8	mmio; /* 0xf4 - 64bit mmio support */
-
-	u8	unused[11];
+	u8	unused[76];

/* ChromeOS specific (0x100-0xfff) */
    chromeos_acpi_t chromeos;
diff --git a/src/soc/intel/broadwell/acpi/globalnvs.asl b/src/soc/intel/broadwell/acpi/globalnvs.asl
index a28ef4b..aa3c344 100644
--- a/src/soc/intel/broadwell/acpi/globalnvs.asl
+++ b/src/soc/intel/broadwell/acpi/globalnvs.asl
@@ -46,48 +46,6 @@
    PM1I,	64,	// 0x20 - 0x27 - PM1 wake status bit
    GPEI,	64,	// 0x28 - 0x2f - GPE wake status bit

-	/* IGD OpRegion */
-	Offset (0xb4),
-	ASLB,	32,	// 0xb4 - IGD OpRegion Base Address
-	IBTT,	 8,	// 0xb8 - IGD boot panel device
-	IPAT,	 8,	// 0xb9 - IGD panel type CMOS option
-	ITVF,	 8,	// 0xba - IGD TV format CMOS option
-	ITVM,	 8,	// 0xbb - IGD TV minor format option
-	IPSC,	 8,	// 0xbc - IGD panel scaling
-	IBLC,	 8,	// 0xbd - IGD BLC config
-	IBIA,	 8,	// 0xbe - IGD BIA config
-	ISSC,	 8,	// 0xbf - IGD SSC config
-	I409,	 8,	// 0xc0 - IGD 0409 modified settings
-	I509,	 8,	// 0xc1 - IGD 0509 modified settings
-	I609,	 8,	// 0xc2 - IGD 0609 modified settings
-	I709,	 8,	// 0xc3 - IGD 0709 modified settings
-	IDMM,	 8,	// 0xc4 - IGD Power conservation feature
-	IDMS,	 8,	// 0xc5 - IGD DVMT memory size
-	IF1E,	 8,	// 0xc6 - IGD function 1 enable
-	HVCO,	 8,	// 0xc7 - IGD HPLL VCO
-	NXD1,	32,	// 0xc8 - IGD _DGS next DID1
-	NXD2,	32,	// 0xcc - IGD _DGS next DID2
-	NXD3,	32,	// 0xd0 - IGD _DGS next DID3
-	NXD4,	32,	// 0xd4 - IGD _DGS next DID4
-	NXD5,	32,	// 0xd8 - IGD _DGS next DID5
-	NXD6,	32,	// 0xdc - IGD _DGS next DID6
-	NXD7,	32,	// 0xe0 - IGD _DGS next DID7
-	NXD8,	32,	// 0xe4 - IGD _DGS next DID8
-
-	ISCI,	 8,	// 0xe8 - IGD SMI/SCI mode (0: SCI)
-	PAVP,	 8,	// 0xe9 - IGD PAVP data
-	Offset (0xeb),
-	OSCC,	 8,	// 0xeb - PCIe OSC control
-	NPCE,	 8,	// 0xec - native PCIe support
-	PLFL,	 8,	// 0xed - platform flavor
-	BREV,	 8,	// 0xee - board revision
-	DPBM,	 8,	// 0xef - digital port b mode
-	DPCM,	 8,	// 0xf0 - digital port c mode
-	DPDM,	 8,	// 0xf1 - digital port d mode
-	ALFP,	 8,	// 0xf2 - active lfp
-	IMON,	 8,	// 0xf3 - current graphics turbo imon value
-	MMIO,	 8,	// 0xf4 - 64bit mmio support
-
    /* ChromeOS specific */
    Offset (0x100),
    #include <vendorcode/google/chromeos/acpi/gnvs.asl>
diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c
index dbb4205..79d0ae5 100644
--- a/src/soc/intel/broadwell/igd.c
+++ b/src/soc/intel/broadwell/igd.c
@@ -492,19 +492,6 @@
    gtt_rmw(0x64810, 0xfffff800, dpdiv);
 }

-uintptr_t gma_get_gnvs_aslb(const void *gnvs)
-{
-	const global_nvs_t *gnvs_ptr = gnvs;
-	return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0);
-}
-
-void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb)
-{
-	global_nvs_t *gnvs_ptr = gnvs;
-	if (gnvs_ptr)
-		gnvs_ptr->aslb = aslb;
-}
-
 static void igd_init(struct device *dev)
 {
    int is_broadwell = !!(cpu_family_model() == BROADWELL_FAMILY_ULT);
@@ -588,32 +575,7 @@
    	gfx_set_init_done(lightup_ok);
    }

-	intel_gma_restore_opregion();
-}
-
-static unsigned long
-gma_write_acpi_tables(struct device *const dev, unsigned long current,
-		struct acpi_rsdp *const rsdp)
-{
-	igd_opregion_t *opregion = (igd_opregion_t *)current;
-	global_nvs_t *gnvs;
-
-	if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS)
-		return current;
-
-	current += sizeof(igd_opregion_t);
-
-	/* GNVS has been already set up */
-	gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
-	if (gnvs) {
-		/* IGD OpRegion Base Address */
-		gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion);
-	} else {
-		printk(BIOS_ERR, "Error: GNVS table not found.\n");
-	}
-
-	current = acpi_align_current(current);
-	return current;
+	intel_gma_init_igd_opregion();
 }

static void gma_generate_ssdt(struct device *dev)
@@ -629,7 +591,6 @@
    .enable_resources	= &pci_dev_enable_resources,
    .init			= &igd_init,
    .ops_pci		= &broadwell_pci_ops,
-	.write_acpi_tables	= gma_write_acpi_tables,
    .acpi_fill_ssdt		= gma_generate_ssdt,
 };

diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h
index b2bc97a..925a699 100644
--- a/src/soc/intel/broadwell/include/soc/nvs.h
+++ b/src/soc/intel/broadwell/include/soc/nvs.h
@@ -39,40 +39,7 @@
    u64	gpei; /* 0x28 - 0x2f - GPE wake status bit */
    u8	unused1[132]; /* 0x30 - 0xb3 - unused */

-	/* IGD OpRegion */
-	u32	aslb; /* 0xb4 - IGD OpRegion Base Address */
-	u8	ibtt; /* 0xb8 - IGD boot type */
-	u8	ipat; /* 0xb9 - IGD panel type */
-	u8	itvf; /* 0xba - IGD TV format */
-	u8	itvm; /* 0xbb - IGD TV minor format */
-	u8	ipsc; /* 0xbc - IGD Panel Scaling */
-	u8	iblc; /* 0xbd - IGD BLC configuration */
-	u8	ibia; /* 0xbe - IGD BIA configuration */
-	u8	issc; /* 0xbf - IGD SSC configuration */
-	u8	i409; /* 0xc0 - IGD 0409 modified settings */
-	u8	i509; /* 0xc1 - IGD 0509 modified settings */
-	u8	i609; /* 0xc2 - IGD 0609 modified settings */
-	u8	i709; /* 0xc3 - IGD 0709 modified settings */
-	u8	idmm; /* 0xc4 - IGD Power Conservation */
-	u8	idms; /* 0xc5 - IGD DVMT memory size */
-	u8	if1e; /* 0xc6 - IGD Function 1 Enable */
-	u8	hvco; /* 0xc7 - IGD HPLL VCO */
-	u32	nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */
-	u8	isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */
-	u8	pavp; /* 0xe9 - IGD PAVP data */
-	u8	rsvd2; /* 0xea - rsvd */
-	u8	oscc; /* 0xeb - PCIe OSC control */
-	u8	npce; /* 0xec - native PCIe support */
-	u8	plfl; /* 0xed - platform flavor */
-	u8	brev; /* 0xee - board revision */
-	u8	dpbm; /* 0xef - digital port b mode */
-	u8	dpcm; /* 0xf0 - digital port c mode */
-	u8	dpdm; /* 0xf1 - digital port c mode */
-	u8	alfp; /* 0xf2 - active lfp */
-	u8	imon; /* 0xf3 - current graphics turbo imon value */
-	u8	mmio; /* 0xf4 - 64bit mmio support */
-
-	u8	unused2[11];
+	u8	unused2[76];

/* ChromeOS specific (0x100 - 0xfff) */
    chromeos_acpi_t chromeos;
diff --git a/src/soc/intel/cannonlake/graphics.c b/src/soc/intel/cannonlake/graphics.c
index 84e9776..9046119 100644
--- a/src/soc/intel/cannonlake/graphics.c
+++ b/src/soc/intel/cannonlake/graphics.c
@@ -72,20 +72,6 @@
    	/* Initialize PCI device, load/execute BIOS Option ROM */
    	pci_dev_init(dev);
    }
-}

-uintptr_t graphics_soc_write_acpi_opregion(struct device *device,
-		uintptr_t current, struct acpi_rsdp *rsdp)
-{
-	igd_opregion_t *opregion;
-
-	printk(BIOS_DEBUG, "ACPI:    * IGD OpRegion\n");
-	opregion = (igd_opregion_t *)current;
-
-	if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS)
-		return current;
-
-	current += sizeof(igd_opregion_t);
-
-	return acpi_align_current(current);
+	intel_gma_init_igd_opregion();
 }
diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c
index 55c181b..0b2d635 100644
--- a/src/soc/intel/common/block/graphics/graphics.c
+++ b/src/soc/intel/common/block/graphics/graphics.c
@@ -132,7 +132,6 @@
    .init			= graphics_soc_init,
    .ops_pci		= &pci_dev_ops_pci,
 #if CONFIG(HAVE_ACPI_TABLES)
-	.write_acpi_tables	= graphics_soc_write_acpi_opregion,
    .acpi_fill_ssdt		= gma_generate_ssdt,
 #endif
    .scan_bus		= scan_generic_bus,
diff --git a/src/soc/intel/common/block/include/intelblocks/graphics.h b/src/soc/intel/common/block/include/intelblocks/graphics.h
index 5a68952..3af5728 100644
--- a/src/soc/intel/common/block/include/intelblocks/graphics.h
+++ b/src/soc/intel/common/block/include/intelblocks/graphics.h
@@ -19,20 +19,6 @@
  */
 void graphics_soc_init(struct device *dev);

-/*
- * Write ASL entry for Graphics opregion
- * Input:
- * struct device *device: device structure
- * current: start address of graphics opregion
- * rsdp: pointer to RSDT (and XSDT) structure
- *
- * Output:
- * End address of graphics opregion so that the called
- * can use the same for future calls to write_acpi_tables
- */
-uintptr_t graphics_soc_write_acpi_opregion(struct device *device,
-		uintptr_t current, struct acpi_rsdp *rsdp);
-
 /* i915 controller info for ACPI backlight controls */
 const struct i915_gpu_controller_info *
 intel_igd_get_controller_info(struct device *device);
diff --git a/src/soc/intel/icelake/graphics.c b/src/soc/intel/icelake/graphics.c
index 0ee340c..ab2fc54 100644
--- a/src/soc/intel/icelake/graphics.c
+++ b/src/soc/intel/icelake/graphics.c
@@ -30,6 +30,11 @@

void graphics_soc_init(struct device *dev)
 {
+	/* IGD needs to Bus Master */
+	uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND);
+	reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
+	pci_write_config32(dev, PCI_COMMAND, reg32);
+
    /*
     * GFX PEIM module inside FSP binary is taking care of graphics
     * initialization based on RUN_FSP_GOP Kconfig
@@ -39,30 +44,12 @@
     * In case of non-FSP solution, SoC need to select VGA_ROM_RUN
     * Kconfig to perform GFX initialization through VGA OpRom.
     */
-	if (CONFIG(RUN_FSP_GOP))
-		return;
+	if (CONFIG(RUN_FSP_GOP)) {
+		/* nothing to do */
+	} else {
+		/* Initialize PCI device, load/execute BIOS Option ROM */
+		pci_dev_init(dev);
+	}

-	/* IGD needs to Bus Master */
-	uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND);
-	reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
-	pci_write_config32(dev, PCI_COMMAND, reg32);
-
-	/* Initialize PCI device, load/execute BIOS Option ROM */
-	pci_dev_init(dev);
-}
-
-uintptr_t graphics_soc_write_acpi_opregion(struct device *device,
-		uintptr_t current, struct acpi_rsdp *rsdp)
-{
-	igd_opregion_t *opregion;
-
-	printk(BIOS_DEBUG, "ACPI:    * IGD OpRegion\n");
-	opregion = (igd_opregion_t *)current;
-
-	if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS)
-		return current;
-
-	current += sizeof(igd_opregion_t);
-
-	return acpi_align_current(current);
+	intel_gma_init_igd_opregion();
 }
diff --git a/src/soc/intel/jasperlake/graphics.c b/src/soc/intel/jasperlake/graphics.c
index 0ee340c..bd9f9d3 100644
--- a/src/soc/intel/jasperlake/graphics.c
+++ b/src/soc/intel/jasperlake/graphics.c
@@ -30,6 +30,11 @@

void graphics_soc_init(struct device *dev)
 {
+	/* IGD needs to Bus Master */
+	uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND);
+	reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
+	pci_write_config32(dev, PCI_COMMAND, reg32);
+
    /*
     * GFX PEIM module inside FSP binary is taking care of graphics
     * initialization based on RUN_FSP_GOP Kconfig
@@ -39,30 +44,13 @@
     * In case of non-FSP solution, SoC need to select VGA_ROM_RUN
     * Kconfig to perform GFX initialization through VGA OpRom.
     */
-	if (CONFIG(RUN_FSP_GOP))
+	if (CONFIG(RUN_FSP_GOP)) {
+		/* nothing to do */
    	return;
+	} else {
+		/* Initialize PCI device, load/execute BIOS Option ROM */
+		pci_dev_init(dev);
+	}

-	/* IGD needs to Bus Master */
-	uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND);
-	reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
-	pci_write_config32(dev, PCI_COMMAND, reg32);
-
-	/* Initialize PCI device, load/execute BIOS Option ROM */
-	pci_dev_init(dev);
-}
-
-uintptr_t graphics_soc_write_acpi_opregion(struct device *device,
-		uintptr_t current, struct acpi_rsdp *rsdp)
-{
-	igd_opregion_t *opregion;
-
-	printk(BIOS_DEBUG, "ACPI:    * IGD OpRegion\n");
-	opregion = (igd_opregion_t *)current;
-
-	if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS)
-		return current;
-
-	current += sizeof(igd_opregion_t);
-
-	return acpi_align_current(current);
+	intel_gma_init_igd_opregion();
 }
diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl
index 7c40630..85d8ff6 100644
--- a/src/soc/intel/skylake/acpi/globalnvs.asl
+++ b/src/soc/intel/skylake/acpi/globalnvs.asl
@@ -60,48 +60,6 @@
    A4GB,	64,	// 0x55 - 0x5C Base of above 4GB MMIO Resource
    A4GS,	64,	// 0x5D - 0x64 Length of above 4GB MMIO Resource

-	/* IGD OpRegion */
-	Offset (0xb4),
-	ASLB,	32,	// 0xb4 - IGD OpRegion Base Address
-	IBTT,	 8,	// 0xb8 - IGD boot panel device
-	IPAT,	 8,	// 0xb9 - IGD panel type CMOS option
-	ITVF,	 8,	// 0xba - IGD TV format CMOS option
-	ITVM,	 8,	// 0xbb - IGD TV minor format option
-	IPSC,	 8,	// 0xbc - IGD panel scaling
-	IBLC,	 8,	// 0xbd - IGD BLC config
-	IBIA,	 8,	// 0xbe - IGD BIA config
-	ISSC,	 8,	// 0xbf - IGD SSC config
-	I409,	 8,	// 0xc0 - IGD 0409 modified settings
-	I509,	 8,	// 0xc1 - IGD 0509 modified settings
-	I609,	 8,	// 0xc2 - IGD 0609 modified settings
-	I709,	 8,	// 0xc3 - IGD 0709 modified settings
-	IDMM,	 8,	// 0xc4 - IGD Power conservation feature
-	IDMS,	 8,	// 0xc5 - IGD DVMT memory size
-	IF1E,	 8,	// 0xc6 - IGD function 1 enable
-	HVCO,	 8,	// 0xc7 - IGD HPLL VCO
-	NXD1,	32,	// 0xc8 - IGD _DGS next DID1
-	NXD2,	32,	// 0xcc - IGD _DGS next DID2
-	NXD3,	32,	// 0xd0 - IGD _DGS next DID3
-	NXD4,	32,	// 0xd4 - IGD _DGS next DID4
-	NXD5,	32,	// 0xd8 - IGD _DGS next DID5
-	NXD6,	32,	// 0xdc - IGD _DGS next DID6
-	NXD7,	32,	// 0xe0 - IGD _DGS next DID7
-	NXD8,	32,	// 0xe4 - IGD _DGS next DID8
-
-	ISCI,	 8,	// 0xe8 - IGD SMI/SCI mode (0: SCI)
-	PAVP,	 8,	// 0xe9 - IGD PAVP data
-	Offset (0xeb),
-	OSCC,	 8,	// 0xeb - PCIe OSC control
-	NPCE,	 8,	// 0xec - native PCIe support
-	PLFL,	 8,	// 0xed - platform flavor
-	BREV,	 8,	// 0xee - board revision
-	DPBM,	 8,	// 0xef - digital port b mode
-	DPCM,	 8,	// 0xf0 - digital port c mode
-	DPDM,	 8,	// 0xf1 - digital port d mode
-	ALFP,	 8,	// 0xf2 - active lfp
-	IMON,	 8,	// 0xf3 - current graphics turbo imon value
-	MMIO,	 8,	// 0xf4 - 64bit mmio support
-
    /* ChromeOS specific */
    Offset (0x100),
    #include <vendorcode/google/chromeos/acpi/gnvs.asl>
diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c
index c338a67..bc9a31b 100644
--- a/src/soc/intel/skylake/graphics.c
+++ b/src/soc/intel/skylake/graphics.c
@@ -125,55 +125,7 @@
    	pci_dev_init(dev);
    }

-	intel_gma_restore_opregion();
-}
-
-uintptr_t gma_get_gnvs_aslb(const void *gnvs)
-{
-	const global_nvs_t *gnvs_ptr = gnvs;
-	return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0);
-}
-
-void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb)
-{
-	global_nvs_t *gnvs_ptr = gnvs;
-	if (gnvs_ptr)
-		gnvs_ptr->aslb = aslb;
-}
-
-/* Initialize IGD OpRegion, called from ACPI code */
-static void update_igd_opregion(igd_opregion_t *opregion)
-{
-	/* FIXME: Add platform specific mailbox initialization */
-}
-
-uintptr_t graphics_soc_write_acpi_opregion(struct device *device,
-		uintptr_t current, struct acpi_rsdp *rsdp)
-{
-	igd_opregion_t *opregion;
-	global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
-
-	/* If GOP is not used, exit here */
-	if (!CONFIG(INTEL_GMA_ADD_VBT))
-		return current;
-
-	/* If IGD is disabled, exit here */
-	if (pci_read_config16(device, PCI_VENDOR_ID) == 0xFFFF)
-		return current;
-
-	printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n");
-	opregion = (igd_opregion_t *)current;
-
-	if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS)
-		return current;
-	if (gnvs)
-		gnvs->aslb = (u32)(uintptr_t)opregion;
-	update_igd_opregion(opregion);
-	current += sizeof(igd_opregion_t);
-	current = acpi_align_current(current);
-
-	printk(BIOS_DEBUG, "current = %lx\n", current);
-	return current;
+	intel_gma_init_igd_opregion();
 }

const struct i915_gpu_controller_info *
diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h
index 480805b..8621106 100644
--- a/src/soc/intel/skylake/include/soc/nvs.h
+++ b/src/soc/intel/skylake/include/soc/nvs.h
@@ -49,42 +49,7 @@
    u8	e4gm; /* 0x54 - Enable above 4GB MMIO Resource */
    u64	a4gb; /* 0x55 - 0x5C Base of above 4GB MMIO Resource */
    u64	a4gs; /* 0x5D - 0x64 Length of above 4GB MMIO Resource */
-	u8	rsvd[79];
-
-	/* IGD OpRegion */
-	u32	aslb; /* 0xb4 - IGD OpRegion Base Address */
-	u8	ibtt; /* 0xb8 - IGD boot type */
-	u8	ipat; /* 0xb9 - IGD panel type */
-	u8	itvf; /* 0xba - IGD TV format */
-	u8	itvm; /* 0xbb - IGD TV minor format */
-	u8	ipsc; /* 0xbc - IGD Panel Scaling */
-	u8	iblc; /* 0xbd - IGD BLC configuration */
-	u8	ibia; /* 0xbe - IGD BIA configuration */
-	u8	issc; /* 0xbf - IGD SSC configuration */
-	u8	i409; /* 0xc0 - IGD 0409 modified settings */
-	u8	i509; /* 0xc1 - IGD 0509 modified settings */
-	u8	i609; /* 0xc2 - IGD 0609 modified settings */
-	u8	i709; /* 0xc3 - IGD 0709 modified settings */
-	u8	idmm; /* 0xc4 - IGD Power Conservation */
-	u8	idms; /* 0xc5 - IGD DVMT memory size */
-	u8	if1e; /* 0xc6 - IGD Function 1 Enable */
-	u8	hvco; /* 0xc7 - IGD HPLL VCO */
-	u32	nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */
-	u8	isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */
-	u8	pavp; /* 0xe9 - IGD PAVP data */
-	u8	rsvd12; /* 0xea - rsvd */
-	u8	oscc; /* 0xeb - PCIe OSC control */
-	u8	npce; /* 0xec - native PCIe support */
-	u8	plfl; /* 0xed - platform flavor */
-	u8	brev; /* 0xee - board revision */
-	u8	dpbm; /* 0xef - digital port b mode */
-	u8	dpcm; /* 0xf0 - digital port c mode */
-	u8	dpdm; /* 0xf1 - digital port c mode */
-	u8	alfp; /* 0xf2 - active lfp */
-	u8	imon; /* 0xf3 - current graphics turbo imon value */
-	u8	mmio; /* 0xf4 - 64bit mmio support */
-
-	u8	unused[11];
+	u8	rsvd[155];

/* ChromeOS specific (0x100 - 0xfff) */
    chromeos_acpi_t chromeos;
diff --git a/src/soc/intel/tigerlake/graphics.c b/src/soc/intel/tigerlake/graphics.c
index 4054bd5..2164338 100644
--- a/src/soc/intel/tigerlake/graphics.c
+++ b/src/soc/intel/tigerlake/graphics.c
@@ -36,6 +36,11 @@

void graphics_soc_init(struct device *dev)
 {
+	/* IGD needs to Bus Master */
+	uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND);
+	reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
+	pci_write_config32(dev, PCI_COMMAND, reg32);
+
    /*
     * GFX PEIM module inside FSP binary is taking care of graphics
     * initialization based on RUN_FSP_GOP Kconfig
@@ -45,30 +50,12 @@
     * In case of non-FSP solution, SoC need to select VGA_ROM_RUN
     * Kconfig to perform GFX initialization through VGA OpRom.
     */
-	if (CONFIG(RUN_FSP_GOP))
-		return;
+	if (CONFIG(RUN_FSP_GOP)) {
+		/* nothing to do */
+	} else {
+		/* Initialize PCI device, load/execute BIOS Option ROM */
+		pci_dev_init(dev);
+	}

-	/* IGD needs to Bus Master */
-	uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND);
-	reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
-	pci_write_config32(dev, PCI_COMMAND, reg32);
-
-	/* Initialize PCI device, load/execute BIOS Option ROM */
-	pci_dev_init(dev);
-}
-
-uintptr_t graphics_soc_write_acpi_opregion(struct device *device,
-		uintptr_t current, struct acpi_rsdp *rsdp)
-{
-	igd_opregion_t *opregion;
-
-	printk(BIOS_DEBUG, "ACPI:    * IGD OpRegion\n");
-	opregion = (igd_opregion_t *)current;
-
-	if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS)
-		return current;
-
-	current += sizeof(igd_opregion_t);
-
-	return acpi_align_current(current);
+	intel_gma_init_igd_opregion();
 }
diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
index 8e99d49..2d42107 100644
--- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
+++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
@@ -109,47 +109,8 @@
    /* XHCI */
    Offset (0xb2),
    XHCI,	 8,
-	/* IGD OpRegion */
-	Offset (0xb4),
-	ASLB,	32,	// 0xb4 - IGD OpRegion Base Address
-	IBTT,	 8,	// 0xb8 - IGD boot panel device
-	IPAT,	 8,	// 0xb9 - IGD panel type CMOS option
-	ITVF,	 8,	// 0xba - IGD TV format CMOS option
-	ITVM,	 8,	// 0xbb - IGD TV minor format option
-	IPSC,	 8,	// 0xbc - IGD panel scaling
-	IBLC,	 8,	// 0xbd - IGD BLC config
-	IBIA,	 8,	// 0xbe - IGD BIA config
-	ISSC,	 8,	// 0xbf - IGD SSC config
-	I409,	 8,	// 0xc0 - IGD 0409 modified settings
-	I509,	 8,	// 0xc1 - IGD 0509 modified settings
-	I609,	 8,	// 0xc2 - IGD 0609 modified settings
-	I709,	 8,	// 0xc3 - IGD 0709 modified settings
-	IDMM,	 8,	// 0xc4 - IGD Power conservation feature
-	IDMS,	 8,	// 0xc5 - IGD DVMT memory size
-	IF1E,	 8,	// 0xc6 - IGD function 1 enable
-	HVCO,	 8,	// 0xc7 - IGD HPLL VCO
-	NXD1,	32,	// 0xc8 - IGD _DGS next DID1
-	NXD2,	32,	// 0xcc - IGD _DGS next DID2
-	NXD3,	32,	// 0xd0 - IGD _DGS next DID3
-	NXD4,	32,	// 0xd4 - IGD _DGS next DID4
-	NXD5,	32,	// 0xd8 - IGD _DGS next DID5
-	NXD6,	32,	// 0xdc - IGD _DGS next DID6
-	NXD7,	32,	// 0xe0 - IGD _DGS next DID7
-	NXD8,	32,	// 0xe4 - IGD _DGS next DID8

-	ISCI,	 8,	// 0xe8 - IGD SMI/SCI mode (0: SCI)
-	PAVP,	 8,	// 0xe9 - IGD PAVP data
-	Offset (0xeb),
-	OSCC,	 8,	// 0xeb - PCIe OSC control
-	NPCE,	 8,	// 0xec - native PCIe support
-	PLFL,	 8,	// 0xed - platform flavor
-	BREV,	 8,	// 0xee - board revision
-	DPBM,	 8,	// 0xef - digital port b mode
-	DPCM,	 8,	// 0xf0 - digital port c mode
-	DPDM,	 8,	// 0xf1 - digital port d mode
-	ALFP,	 8,	// 0xf2 - active lfp
-	IMON,	 8,	// 0xf3 - current graphics turbo imon value
-	MMIO,	 8,	// 0xf4 - 64bit mmio support
+	Offset (0xf5),
    TPIQ,	 8,	// 0xf5 - trackpad IRQ value

/* ChromeOS specific */
diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h
index 25c392d..8cb07b8 100644
--- a/src/southbridge/intel/bd82x6x/nvs.h
+++ b/src/southbridge/intel/bd82x6x/nvs.h
@@ -97,38 +97,7 @@
    u8	rsvd11[6];
    /* XHCI */
    u8	xhci;
-	/* IGD OpRegion (not implemented yet) */
-	u32	aslb; /* 0xb4 - IGD OpRegion Base Address */
-	u8	ibtt; /* 0xb8 - IGD boot type */
-	u8	ipat; /* 0xb9 - IGD panel type */
-	u8	itvf; /* 0xba - IGD TV format */
-	u8	itvm; /* 0xbb - IGD TV minor format */
-	u8	ipsc; /* 0xbc - IGD Panel Scaling */
-	u8	iblc; /* 0xbd - IGD BLC configuration */
-	u8	ibia; /* 0xbe - IGD BIA configuration */
-	u8	issc; /* 0xbf - IGD SSC configuration */
-	u8	i409; /* 0xc0 - IGD 0409 modified settings */
-	u8	i509; /* 0xc1 - IGD 0509 modified settings */
-	u8	i609; /* 0xc2 - IGD 0609 modified settings */
-	u8	i709; /* 0xc3 - IGD 0709 modified settings */
-	u8	idmm; /* 0xc4 - IGD Power Conservation */
-	u8	idms; /* 0xc5 - IGD DVMT memory size */
-	u8	if1e; /* 0xc6 - IGD Function 1 Enable */
-	u8	hvco; /* 0xc7 - IGD HPLL VCO */
-	u32	nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */
-	u8	isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */
-	u8	pavp; /* 0xe9 - IGD PAVP data */
-	u8	rsvd12; /* 0xea - rsvd */
-	u8	oscc; /* 0xeb - PCIe OSC control */
-	u8	npce; /* 0xec - native PCIe support */
-	u8	plfl; /* 0xed - platform flavor */
-	u8	brev; /* 0xee - board revision */
-	u8	dpbm; /* 0xef - digital port b mode */
-	u8	dpcm; /* 0xf0 - digital port c mode */
-	u8	dpdm; /* 0xf1 - digital port c mode */
-	u8	alfp; /* 0xf2 - active lfp */
-	u8	imon; /* 0xf3 - current graphics turbo imon value */
-	u8	mmio; /* 0xf4 - 64bit mmio support */
+	u8	rsvd12[65];
    u8	tpiq; /* 0xf5 - trackpad IRQ value */
    u8	rsvd13[10]; /* 0xf6 - rsvd */

diff --git a/src/southbridge/intel/i82801dx/nvs.h b/src/southbridge/intel/i82801dx/nvs.h
index c556573..75e0d0d 100644
--- a/src/southbridge/intel/i82801dx/nvs.h
+++ b/src/southbridge/intel/i82801dx/nvs.h
@@ -91,27 +91,7 @@
    u8	gtf2[7];
    u8	idem;
    u8	idet;
-	u8	rsvd11[7];
-	/* IGD OpRegion (not implemented yet) */
-	u32	aslb; /* 0xb4 - IGD OpRegion Base Address */
-	u8	ibtt;
-	u8	ipat;
-	u8	itvf;
-	u8	itvm;
-	u8	ipsc;
-	u8	iblc;
-	u8	ibia;
-	u8	issc;
-	u8	i409;
-	u8	i509;
-	u8	i609;
-	u8	i709;
-	u8	idmm;
-	u8	idms;
-	u8	if1e;
-	u8	hvco;
-	u32	nxd[8];
-	u8	rsvd12[8];
+	u8	rsvd11[67];
    /* Mainboard specific */
    u8	dock; /* 0xf0 - Docking Status */
    u8	bten;
diff --git a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl
index d71b1e0..4f3abeb 100644
--- a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl
+++ b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl
@@ -105,33 +105,6 @@
    GTF2,	56,	// 0xa4 - GTF task file buffer for port 2
    IDEM,	 8,	// 0xab - IDE mode (compatible / enhanced)
    IDET,	 8,	// 0xac - IDE
-	/* IGD OpRegion */
-	Offset (0xb4),
-	ASLB,	32,	// 0xb4 - IGD OpRegion Base Address
-	IBTT,	 8,	// 0xb8 - IGD boot panel device
-	IPAT,	 8,	// 0xb9 - IGD panel type CMOS option
-	ITVF,	 8,	// 0xba - IGD TV format CMOS option
-	ITVM,	 8,	// 0xbb - IGD TV minor format option
-	IPSC,	 8,	// 0xbc - IGD panel scaling
-	IBLC,	 8,	// 0xbd - IGD BLC config
-	IBIA,	 8,	// 0xbe - IGD BIA config
-	ISSC,	 8,	// 0xbf - IGD SSC config
-	I409,	 8,	// 0xc0 - IGD 0409 modified settings
-	I509,	 8,	// 0xc1 - IGD 0509 modified settings
-	I609,	 8,	// 0xc2 - IGD 0609 modified settings
-	I709,	 8,	// 0xc3 - IGD 0709 modified settings
-	IDMM,	 8,	// 0xc4 - IGD DVMT Mode
-	IDMS,	 8,	// 0xc5 - IGD DVMT memory size
-	IF1E,	 8,	// 0xc6 - IGD function 1 enable
-	HVCO,	 8,	// 0xc7 - IGD HPLL VCO
-	NXD1,	32,	// 0xc8 - IGD _DGS next DID1
-	NXD2,	32,	// 0xcc - IGD _DGS next DID2
-	NXD3,	32,	// 0xd0 - IGD _DGS next DID3
-	NXD4,	32,	// 0xd4 - IGD _DGS next DID4
-	NXD5,	32,	// 0xd8 - IGD _DGS next DID5
-	NXD6,	32,	// 0xdc - IGD _DGS next DID6
-	NXD7,	32,	// 0xe0 - IGD _DGS next DID7
-	NXD8,	32,	// 0xe4 - IGD _DGS next DID8
    /* Mainboard Specific (TODO move elsewhere) */
    Offset (0xf0),
    DOCK,	 8,	// 0xf0 - Docking Status
diff --git a/src/southbridge/intel/i82801gx/nvs.h b/src/southbridge/intel/i82801gx/nvs.h
index 980ab0b..0ddaf07 100644
--- a/src/southbridge/intel/i82801gx/nvs.h
+++ b/src/southbridge/intel/i82801gx/nvs.h
@@ -90,27 +90,7 @@
    u8	gtf2[7];
    u8	idem;
    u8	idet;
-	u8	rsvd11[7];
-	/* IGD OpRegion (not implemented yet) */
-	u32	aslb; /* 0xb4 - IGD OpRegion Base Address */
-	u8	ibtt;
-	u8	ipat;
-	u8	itvf;
-	u8	itvm;
-	u8	ipsc;
-	u8	iblc;
-	u8	ibia;
-	u8	issc;
-	u8	i409;
-	u8	i509;
-	u8	i609;
-	u8	i709;
-	u8	idmm;
-	u8	idms;
-	u8	if1e;
-	u8	hvco;
-	u32	nxd[8];
-	u8	rsvd12[8];
+	u8	rsvd11[67];
    /* Mainboard specific */
    u8	dock; /* 0xf0 - Docking Status */
    u8	bten;
diff --git a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl
index 6778fe7..a9824d2 100644
--- a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl
+++ b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl
@@ -109,33 +109,6 @@
    GTF2,	56,	// 0xa4 - GTF task file buffer for port 2
    IDEM,	 8,	// 0xab - IDE mode (compatible / enhanced)
    IDET,	 8,	// 0xac - IDE
-	/* IGD OpRegion */
-	Offset (0xb4),
-	ASLB,	32,	// 0xb4 - IGD OpRegion Base Address
-	IBTT,	 8,	// 0xb8 - IGD boot panel device
-	IPAT,	 8,	// 0xb9 - IGD panel type CMOS option
-	ITVF,	 8,	// 0xba - IGD TV format CMOS option
-	ITVM,	 8,	// 0xbb - IGD TV minor format option
-	IPSC,	 8,	// 0xbc - IGD panel scaling
-	IBLC,	 8,	// 0xbd - IGD BLC config
-	IBIA,	 8,	// 0xbe - IGD BIA config
-	ISSC,	 8,	// 0xbf - IGD SSC config
-	I409,	 8,	// 0xc0 - IGD 0409 modified settings
-	I509,	 8,	// 0xc1 - IGD 0509 modified settings
-	I609,	 8,	// 0xc2 - IGD 0609 modified settings
-	I709,	 8,	// 0xc3 - IGD 0709 modified settings
-	IDMM,	 8,	// 0xc4 - IGD DVMT Mode
-	IDMS,	 8,	// 0xc5 - IGD DVMT memory size
-	IF1E,	 8,	// 0xc6 - IGD function 1 enable
-	HVCO,	 8,	// 0xc7 - IGD HPLL VCO
-	NXD1,	32,	// 0xc8 - IGD _DGS next DID1
-	NXD2,	32,	// 0xcc - IGD _DGS next DID2
-	NXD3,	32,	// 0xd0 - IGD _DGS next DID3
-	NXD4,	32,	// 0xd4 - IGD _DGS next DID4
-	NXD5,	32,	// 0xd8 - IGD _DGS next DID5
-	NXD6,	32,	// 0xdc - IGD _DGS next DID6
-	NXD7,	32,	// 0xe0 - IGD _DGS next DID7
-	NXD8,	32,	// 0xe4 - IGD _DGS next DID8
    /* Mainboard Specific (TODO move elsewhere) */
    Offset (0xf0),
    DOCK,	 8,	// 0xf0 - Docking Status
diff --git a/src/southbridge/intel/i82801ix/nvs.h b/src/southbridge/intel/i82801ix/nvs.h
index 0954daa..d1d3a73 100644
--- a/src/southbridge/intel/i82801ix/nvs.h
+++ b/src/southbridge/intel/i82801ix/nvs.h
@@ -92,27 +92,7 @@
    u8	gtf2[7];
    u8	idem;
    u8	idet;
-	u8	rsvd11[7];
-	/* IGD OpRegion (not implemented yet) */
-	u32	aslb; /* 0xb4 - IGD OpRegion Base Address */
-	u8	ibtt;
-	u8	ipat;
-	u8	itvf;
-	u8	itvm;
-	u8	ipsc;
-	u8	iblc;
-	u8	ibia;
-	u8	issc;
-	u8	i409;
-	u8	i509;
-	u8	i609;
-	u8	i709;
-	u8	idmm;
-	u8	idms;
-	u8	if1e;
-	u8	hvco;
-	u32	nxd[8];
-	u8	rsvd12[8];
+	u8	rsvd11[67];
    /* Mainboard specific */
    u8	dock; /* 0xf0 - Docking Status */
    u8	bten;
diff --git a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl
index ce810eb..dbc23b4 100644
--- a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl
+++ b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl
@@ -109,33 +109,6 @@
    GTF2,	56,	// 0xa4 - GTF task file buffer for port 2
    IDEM,	 8,	// 0xab - IDE mode (compatible / enhanced)
    IDET,	 8,	// 0xac - IDE
-	/* IGD OpRegion */
-	Offset (0xb4),
-	ASLB,	32,	// 0xb4 - IGD OpRegion Base Address
-	IBTT,	 8,	// 0xb8 - IGD boot panel device
-	IPAT,	 8,	// 0xb9 - IGD panel type CMOS option
-	ITVF,	 8,	// 0xba - IGD TV format CMOS option
-	ITVM,	 8,	// 0xbb - IGD TV minor format option
-	IPSC,	 8,	// 0xbc - IGD panel scaling
-	IBLC,	 8,	// 0xbd - IGD BLC config
-	IBIA,	 8,	// 0xbe - IGD BIA config
-	ISSC,	 8,	// 0xbf - IGD SSC config
-	I409,	 8,	// 0xc0 - IGD 0409 modified settings
-	I509,	 8,	// 0xc1 - IGD 0509 modified settings
-	I609,	 8,	// 0xc2 - IGD 0609 modified settings
-	I709,	 8,	// 0xc3 - IGD 0709 modified settings
-	IDMM,	 8,	// 0xc4 - IGD DVMT Mode
-	IDMS,	 8,	// 0xc5 - IGD DVMT memory size
-	IF1E,	 8,	// 0xc6 - IGD function 1 enable
-	HVCO,	 8,	// 0xc7 - IGD HPLL VCO
-	NXD1,	32,	// 0xc8 - IGD _DGS next DID1
-	NXD2,	32,	// 0xcc - IGD _DGS next DID2
-	NXD3,	32,	// 0xd0 - IGD _DGS next DID3
-	NXD4,	32,	// 0xd4 - IGD _DGS next DID4
-	NXD5,	32,	// 0xd8 - IGD _DGS next DID5
-	NXD6,	32,	// 0xdc - IGD _DGS next DID6
-	NXD7,	32,	// 0xe0 - IGD _DGS next DID7
-	NXD8,	32,	// 0xe4 - IGD _DGS next DID8
    /* Mainboard Specific (TODO move elsewhere) */
    Offset (0xf0),
    DOCK,	 8,	// 0xf0 - Docking Status
diff --git a/src/southbridge/intel/i82801jx/nvs.h b/src/southbridge/intel/i82801jx/nvs.h
index 95bfa26..82b1b1e 100644
--- a/src/southbridge/intel/i82801jx/nvs.h
+++ b/src/southbridge/intel/i82801jx/nvs.h
@@ -90,27 +90,7 @@
    u8	gtf2[7];
    u8	idem;
    u8	idet;
-	u8	rsvd11[7];
-	/* IGD OpRegion (not implemented yet) */
-	u32	aslb; /* 0xb4 - IGD OpRegion Base Address */
-	u8	ibtt;
-	u8	ipat;
-	u8	itvf;
-	u8	itvm;
-	u8	ipsc;
-	u8	iblc;
-	u8	ibia;
-	u8	issc;
-	u8	i409;
-	u8	i509;
-	u8	i609;
-	u8	i709;
-	u8	idmm;
-	u8	idms;
-	u8	if1e;
-	u8	hvco;
-	u32	nxd[8];
-	u8	rsvd12[8];
+	u8	rsvd11[67];
    /* Mainboard specific */
    u8	dock; /* 0xf0 - Docking Status */
    u8	bten;
diff --git a/src/southbridge/intel/ibexpeak/nvs.h b/src/southbridge/intel/ibexpeak/nvs.h
index c091b6f..bd02ec3 100644
--- a/src/southbridge/intel/ibexpeak/nvs.h
+++ b/src/southbridge/intel/ibexpeak/nvs.h
@@ -96,39 +96,7 @@
    u8	rsvd11[6];
    /* XHCI */
    u8	xhci;
-	/* IGD OpRegion (not implemented yet) */
-	u32	aslb; /* 0xb4 - IGD OpRegion Base Address */
-	u8	ibtt; /* 0xb8 - IGD boot type */
-	u8	ipat; /* 0xb9 - IGD panel type */
-	u8	itvf; /* 0xba - IGD TV format */
-	u8	itvm; /* 0xbb - IGD TV minor format */
-	u8	ipsc; /* 0xbc - IGD Panel Scaling */
-	u8	iblc; /* 0xbd - IGD BLC configuration */
-	u8	ibia; /* 0xbe - IGD BIA configuration */
-	u8	issc; /* 0xbf - IGD SSC configuration */
-	u8	i409; /* 0xc0 - IGD 0409 modified settings */
-	u8	i509; /* 0xc1 - IGD 0509 modified settings */
-	u8	i609; /* 0xc2 - IGD 0609 modified settings */
-	u8	i709; /* 0xc3 - IGD 0709 modified settings */
-	u8	idmm; /* 0xc4 - IGD Power Conservation */
-	u8	idms; /* 0xc5 - IGD DVMT memory size */
-	u8	if1e; /* 0xc6 - IGD Function 1 Enable */
-	u8	hvco; /* 0xc7 - IGD HPLL VCO */
-	u32	nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */
-	u8	isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */
-	u8	pavp; /* 0xe9 - IGD PAVP data */
-	u8	rsvd12; /* 0xea - rsvd */
-	u8	oscc; /* 0xeb - PCIe OSC control */
-	u8	npce; /* 0xec - native PCIe support */
-	u8	plfl; /* 0xed - platform flavor */
-	u8	brev; /* 0xee - board revision */
-	u8	dpbm; /* 0xef - digital port b mode */
-	u8	dpcm; /* 0xf0 - digital port c mode */
-	u8	dpdm; /* 0xf1 - digital port c mode */
-	u8	alfp; /* 0xf2 - active lfp */
-	u8	imon; /* 0xf3 - current graphics turbo imon value */
-	u8	mmio; /* 0xf4 - 64bit mmio support */
-	u8	rsvd13[11]; /* 0xf5 - rsvd */
+	u8	rsvd13[76]; /* 0xf5 - rsvd */

/* ChromeOS specific (starts at 0x100)*/
    chromeos_acpi_t chromeos;
diff --git a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl
index ad7df7f..12e3950 100644
--- a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl
+++ b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl
@@ -104,48 +104,6 @@
    Offset (0xa0),
    CBMC, 32,	// 0xa0 - coreboot mem console pointer

-	/* IGD OpRegion */
-	Offset (0xb4),
-	ASLB,	32,	// 0xb4 - IGD OpRegion Base Address
-	IBTT,	 8,	// 0xb8 - IGD boot panel device
-	IPAT,	 8,	// 0xb9 - IGD panel type CMOS option
-	ITVF,	 8,	// 0xba - IGD TV format CMOS option
-	ITVM,	 8,	// 0xbb - IGD TV minor format option
-	IPSC,	 8,	// 0xbc - IGD panel scaling
-	IBLC,	 8,	// 0xbd - IGD BLC config
-	IBIA,	 8,	// 0xbe - IGD BIA config
-	ISSC,	 8,	// 0xbf - IGD SSC config
-	I409,	 8,	// 0xc0 - IGD 0409 modified settings
-	I509,	 8,	// 0xc1 - IGD 0509 modified settings
-	I609,	 8,	// 0xc2 - IGD 0609 modified settings
-	I709,	 8,	// 0xc3 - IGD 0709 modified settings
-	IDMM,	 8,	// 0xc4 - IGD Power conservation feature
-	IDMS,	 8,	// 0xc5 - IGD DVMT memory size
-	IF1E,	 8,	// 0xc6 - IGD function 1 enable
-	HVCO,	 8,	// 0xc7 - IGD HPLL VCO
-	NXD1,	32,	// 0xc8 - IGD _DGS next DID1
-	NXD2,	32,	// 0xcc - IGD _DGS next DID2
-	NXD3,	32,	// 0xd0 - IGD _DGS next DID3
-	NXD4,	32,	// 0xd4 - IGD _DGS next DID4
-	NXD5,	32,	// 0xd8 - IGD _DGS next DID5
-	NXD6,	32,	// 0xdc - IGD _DGS next DID6
-	NXD7,	32,	// 0xe0 - IGD _DGS next DID7
-	NXD8,	32,	// 0xe4 - IGD _DGS next DID8
-
-	ISCI,	 8,	// 0xe8 - IGD SMI/SCI mode (0: SCI)
-	PAVP,	 8,	// 0xe9 - IGD PAVP data
-	Offset (0xeb),
-	OSCC,	 8,	// 0xeb - PCIe OSC control
-	NPCE,	 8,	// 0xec - native PCIe support
-	PLFL,	 8,	// 0xed - platform flavor
-	BREV,	 8,	// 0xee - board revision
-	DPBM,	 8,	// 0xef - digital port b mode
-	DPCM,	 8,	// 0xf0 - digital port c mode
-	DPDM,	 8,	// 0xf1 - digital port d mode
-	ALFP,	 8,	// 0xf2 - active lfp
-	IMON,	 8,	// 0xf3 - current graphics turbo imon value
-	MMIO,	 8,	// 0xf4 - 64bit mmio support
-
    /* ChromeOS specific */
    Offset (0x100),
    #include <vendorcode/google/chromeos/acpi/gnvs.asl>
diff --git a/src/southbridge/intel/lynxpoint/nvs.h b/src/southbridge/intel/lynxpoint/nvs.h
index c35b4b5..ff0ea27 100644
--- a/src/southbridge/intel/lynxpoint/nvs.h
+++ b/src/southbridge/intel/lynxpoint/nvs.h
@@ -73,40 +73,7 @@
    u32	s0b[8]; /* 0x60 - 0x7f - BAR0 */
    u32	s1b[8]; /* 0x80 - 0x9f - BAR1 */
    u32	cbmc;   /* 0xa0 - 0xa3 - coreboot memconsole */
-	u8	rsvd6[16];
-	/* IGD OpRegion (not implemented yet) */
-	u32	aslb; /* 0xb4 - IGD OpRegion Base Address */
-	u8	ibtt; /* 0xb8 - IGD boot type */
-	u8	ipat; /* 0xb9 - IGD panel type */
-	u8	itvf; /* 0xba - IGD TV format */
-	u8	itvm; /* 0xbb - IGD TV minor format */
-	u8	ipsc; /* 0xbc - IGD Panel Scaling */
-	u8	iblc; /* 0xbd - IGD BLC configuration */
-	u8	ibia; /* 0xbe - IGD BIA configuration */
-	u8	issc; /* 0xbf - IGD SSC configuration */
-	u8	i409; /* 0xc0 - IGD 0409 modified settings */
-	u8	i509; /* 0xc1 - IGD 0509 modified settings */
-	u8	i609; /* 0xc2 - IGD 0609 modified settings */
-	u8	i709; /* 0xc3 - IGD 0709 modified settings */
-	u8	idmm; /* 0xc4 - IGD Power Conservation */
-	u8	idms; /* 0xc5 - IGD DVMT memory size */
-	u8	if1e; /* 0xc6 - IGD Function 1 Enable */
-	u8	hvco; /* 0xc7 - IGD HPLL VCO */
-	u32	nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */
-	u8	isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */
-	u8	pavp; /* 0xe9 - IGD PAVP data */
-	u8	rsvd12; /* 0xea - rsvd */
-	u8	oscc; /* 0xeb - PCIe OSC control */
-	u8	npce; /* 0xec - native PCIe support */
-	u8	plfl; /* 0xed - platform flavor */
-	u8	brev; /* 0xee - board revision */
-	u8	dpbm; /* 0xef - digital port b mode */
-	u8	dpcm; /* 0xf0 - digital port c mode */
-	u8	dpdm; /* 0xf1 - digital port c mode */
-	u8	alfp; /* 0xf2 - active lfp */
-	u8	imon; /* 0xf3 - current graphics turbo imon value */
-	u8	mmio; /* 0xf4 - 64bit mmio support */
-	u8	rsvd13[11]; /* 0xf5 - rsvd */
+	u8	rsvd6[92];

/* ChromeOS specific (starts at 0x100)*/
    chromeos_acpi_t chromeos;