[coreboot-gerrit] Change in coreboot[master]: device: Give `pci_ops.set_L1_ss_latency` a proper name

[Nico Huber (Code Review)]

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51326 )

Change subject: device: Give `pci_ops.set_L1_ss_latency` a proper name
......................................................................

device: Give `pci_ops.set_L1_ss_latency` a proper name

Rename `set_L1_ss_latency` to what it does: `set_ltr_max_latencies`.

TEST=Built google/brya0 with BUILD_TIMELESS=1: no changes.

Change-Id: I7008aa18bf80d6709dce1b2d3bfbb5ea407a0574
Signed-off-by: Nico Huber 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51326
Reviewed-by: Angel Pons 
Reviewed-by: Aaron Durbin 
Reviewed-by: Furquan Shaikh 
Tested-by: build bot (Jenkins) 
---
M src/device/pciexp_device.c
M src/include/device/pci.h
M src/soc/intel/broadwell/pch/pcie.c
M src/soc/intel/common/block/pcie/pcie.c
4 files changed, 7 insertions(+), 7 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Aaron Durbin: Looks good to me, approved
  Furquan Shaikh: Looks good to me, approved
  Angel Pons: Looks good to me, approved

diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c
index 8d4bb98..3153e0e 100644
--- a/src/device/pciexp_device.c
+++ b/src/device/pciexp_device.c
@@ -132,8 +132,8 @@
    unsigned int cap;
    cap = pciexp_find_extended_cap(dev, PCIE_EXT_CAP_LTR_ID);
    if ((cap) && (root->ops->ops_pci != NULL) &&
-		(root->ops->ops_pci->set_L1_ss_latency != NULL))
-			root->ops->ops_pci->set_L1_ss_latency(dev, cap + 4);
+		(root->ops->ops_pci->set_ltr_max_latencies != NULL))
+			root->ops->ops_pci->set_ltr_max_latencies(dev, cap + 4);
 }

static bool pciexp_is_ltr_supported(struct device *dev, unsigned int cap)
diff --git a/src/include/device/pci.h b/src/include/device/pci.h
index 045eec1..e80cb22 100644
--- a/src/include/device/pci.h
+++ b/src/include/device/pci.h
@@ -31,7 +31,7 @@
    /* set the Subsystem IDs for the PCI device */
    void (*set_subsystem)(struct device *dev, unsigned int vendor,
    	unsigned int device);
-	void (*set_L1_ss_latency)(struct device *dev, unsigned int off);
+	void (*set_ltr_max_latencies)(struct device *dev, unsigned int off);
 };

struct pci_driver {
diff --git a/src/soc/intel/broadwell/pch/pcie.c b/src/soc/intel/broadwell/pch/pcie.c
index 7f16cb4..05619f8 100644
--- a/src/soc/intel/broadwell/pch/pcie.c
+++ b/src/soc/intel/broadwell/pch/pcie.c
@@ -609,7 +609,7 @@
    	root_port_commit_config();
 }

-static void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int off)
+static void pcie_set_ltr_max_latencies(struct device *dev, unsigned int off)
 {
    /* Set max snoop and non-snoop latency for Broadwell */
    pci_write_config32(dev, off,
@@ -619,7 +619,7 @@

static struct pci_operations pcie_ops = {
    .set_subsystem = pci_dev_set_subsystem,
-	.set_L1_ss_latency = pcie_set_L1_ss_max_latency,
+	.set_ltr_max_latencies = pcie_set_ltr_max_latencies,
 };

static struct device_operations device_ops = {
diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c
index 4f5687f..346c0ff 100644
--- a/src/soc/intel/common/block/pcie/pcie.c
+++ b/src/soc/intel/common/block/pcie/pcie.c
@@ -45,7 +45,7 @@
    pci_write_config16(dev, PCI_SEC_STATUS, reg16);
 }

-static void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int offset)
+static void pcie_set_ltr_max_latencies(struct device *dev, unsigned int offset)
 {
    /* Set max snoop and non-snoop latency for the SOC */
    pci_write_config32(dev, offset,
@@ -54,7 +54,7 @@
 }

static struct pci_operations pcie_ops = {
-	.set_L1_ss_latency = pcie_set_L1_ss_max_latency,
+	.set_ltr_max_latencies = pcie_set_ltr_max_latencies,
    .set_subsystem = pci_dev_set_subsystem,
 };