Attention is currently required from: Evgeny Zinoviev. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60221 )
Change subject: [WIP, NOT WORKING YET] mb/apple/imac11_2: Add iMac 21.5-inch, Mid 2010 ......................................................................
[WIP, NOT WORKING YET] mb/apple/imac11_2: Add iMac 21.5-inch, Mid 2010
Add support for the Apple 820-2784 mainboard, which can be found in the 21.5-inch Mid 2010 iMac. This system has a LGA1156 socket for Clarkdale CPUs (Lynnfield CPUs not tested), 4 DDR3 SO-DIMM slots and an Ibex Peak P55 PCH (iGPU is unused).
However, even though coreboot already supports the mobile counterparts of these chips, the Ironlake northbridge code fails spectacularly: QPI initialisation renders the system so unstable that it can't even start doing raminit. Even after fixing this with [1], raminit still needs to be adapted to support Clarkdale, as well as 2 DIMMs per channel. There will be lots of magic involved.
[1]: https://review.coreboot.org/60216
Change-Id: I7d5f5bacabb71d02ad3a036a82466b55ad24f8dc Signed-off-by: Angel Pons th3fanbus@gmail.com --- A src/mainboard/apple/imac11_2/Kconfig A src/mainboard/apple/imac11_2/Kconfig.name A src/mainboard/apple/imac11_2/Makefile.inc A src/mainboard/apple/imac11_2/acpi/ec.asl A src/mainboard/apple/imac11_2/acpi/platform.asl A src/mainboard/apple/imac11_2/acpi/superio.asl A src/mainboard/apple/imac11_2/board_info.txt A src/mainboard/apple/imac11_2/devicetree.cb A src/mainboard/apple/imac11_2/die.c A src/mainboard/apple/imac11_2/dsdt.asl A src/mainboard/apple/imac11_2/gpio.c A src/mainboard/apple/imac11_2/hda_verb.c A src/mainboard/apple/imac11_2/romstage.c 13 files changed, 385 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/60221/1
diff --git a/src/mainboard/apple/imac11_2/Kconfig b/src/mainboard/apple/imac11_2/Kconfig new file mode 100644 index 0000000..96041a5 --- /dev/null +++ b/src/mainboard/apple/imac11_2/Kconfig @@ -0,0 +1,20 @@ +if BOARD_APPLE_IMAC11_2 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_4096 + select NORTHBRIDGE_INTEL_IRONLAKE + select SOUTHBRIDGE_INTEL_IBEXPEAK + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + +config MAINBOARD_DIR + default "apple/imac11_2" + +config MAINBOARD_PART_NUMBER + default "iMac11,2" + +config DRAM_RESET_GATE_GPIO + default 28 + +endif diff --git a/src/mainboard/apple/imac11_2/Kconfig.name b/src/mainboard/apple/imac11_2/Kconfig.name new file mode 100644 index 0000000..11a2451 --- /dev/null +++ b/src/mainboard/apple/imac11_2/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_APPLE_IMAC11_2 + bool "iMac11,2" diff --git a/src/mainboard/apple/imac11_2/Makefile.inc b/src/mainboard/apple/imac11_2/Makefile.inc new file mode 100644 index 0000000..713de4a --- /dev/null +++ b/src/mainboard/apple/imac11_2/Makefile.inc @@ -0,0 +1,4 @@ +bootblock-y += gpio.c +romstage-y += gpio.c + +all-y += die.c diff --git a/src/mainboard/apple/imac11_2/acpi/ec.asl b/src/mainboard/apple/imac11_2/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/apple/imac11_2/acpi/ec.asl diff --git a/src/mainboard/apple/imac11_2/acpi/platform.asl b/src/mainboard/apple/imac11_2/acpi/platform.asl new file mode 100644 index 0000000..aff432b --- /dev/null +++ b/src/mainboard/apple/imac11_2/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/apple/imac11_2/acpi/superio.asl b/src/mainboard/apple/imac11_2/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/apple/imac11_2/acpi/superio.asl diff --git a/src/mainboard/apple/imac11_2/board_info.txt b/src/mainboard/apple/imac11_2/board_info.txt new file mode 100644 index 0000000..be6bff8 --- /dev/null +++ b/src/mainboard/apple/imac11_2/board_info.txt @@ -0,0 +1,4 @@ +Category: desktop +ROM protocol: SPI +Flashrom support: n +FIXME: check category, , put ROM package, ROM socketed, Release year diff --git a/src/mainboard/apple/imac11_2/devicetree.cb b/src/mainboard/apple/imac11_2/devicetree.cb new file mode 100644 index 0000000..47f4305 --- /dev/null +++ b/src/mainboard/apple/imac11_2/devicetree.cb @@ -0,0 +1,49 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/ironlake + + device cpu_cluster 0 on + chip cpu/intel/model_2065x + device lapic 0 on end + end + end + + device domain 0 on + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PCIe graphics + device pci 02.0 off end # iGPU + + chip southbridge/intel/ibexpeak + register "sata_port_map" = "0x3f" + + #register "gpe0_en" = "0x01800046" + #register "alt_gp_smi_en" = "0x0000" + #register "gen1_dec" = "0x040069" + + device pci 16.0 on end # MEI #1 + device pci 16.1 off end # MEI #2 + device pci 16.2 off end # ME IDE-R + device pci 16.3 off end # ME KT + device pci 19.0 off end # Intel GbE + device pci 1a.0 on end # EHCI #2 + device pci 1b.0 on end # HD Audio + device pci 1c.0 on end # RP #1 + device pci 1c.1 on end # RP #2 + device pci 1c.2 on end # RP #3 + device pci 1c.3 on end # RP #4 + device pci 1c.4 on end # RP #5 + device pci 1c.5 on end # RP #6 + device pci 1c.6 on end # RP #7 + device pci 1c.7 on end # RP #8 + device pci 1d.0 on end # EHCI #1 + device pci 1e.0 on end # Conventional PCI bridge + device pci 1f.0 on # LPC bridge + end + device pci 1f.2 on end # SATA (AHCI) + device pci 1f.3 on end # SMBus + device pci 1f.4 off end # Performance Counters + device pci 1f.5 off end # SATA (Legacy) + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/apple/imac11_2/die.c b/src/mainboard/apple/imac11_2/die.c new file mode 100644 index 0000000..4a0818a --- /dev/null +++ b/src/mainboard/apple/imac11_2/die.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <northbridge/intel/ironlake/ironlake.h> +#include <types.h> + +void die_notify(void) +{ + for (unsigned int i = 0; i < 0x4000; i += 4) { + const u32 r = mchbar_read32(i); + if (r) + printk(BIOS_DEBUG, "0x%04x: 0x%08x\n", i, r); + } +} diff --git a/src/mainboard/apple/imac11_2/dsdt.asl b/src/mainboard/apple/imac11_2/dsdt.asl new file mode 100644 index 0000000..6886c06 --- /dev/null +++ b/src/mainboard/apple/imac11_2/dsdt.asl @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20140108 /* OEM revision */ +) +{ + #include <acpi/dsdt_top.asl> + #include <southbridge/intel/common/acpi/platform.asl> + + #include "acpi/platform.asl" + + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (_SB) + { + Device (PCI0) + { + #include <northbridge/intel/ironlake/acpi/ironlake.asl> + + /* TBD: Remove. */ + Name(\XHCI, 0) + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } + #include <northbridge/intel/ironlake/acpi/uncore.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/mainboard/apple/imac11_2/gpio.c b/src/mainboard/apple/imac11_2/gpio.c new file mode 100644 index 0000000..84a9f91 --- /dev/null +++ b/src/mainboard/apple/imac11_2/gpio.c @@ -0,0 +1,199 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_NATIVE, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio1 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio29 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio12 = GPIO_LEVEL_LOW, + .gpio16 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio5 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio11 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_GPIO, + .gpio41 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_GPIO, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_OUTPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_OUTPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_HIGH, + .gpio36 = GPIO_LEVEL_LOW, + .gpio45 = GPIO_LEVEL_LOW, + .gpio48 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_NATIVE, + .gpio69 = GPIO_MODE_NATIVE, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/apple/imac11_2/hda_verb.c b/src/mainboard/apple/imac11_2/hda_verb.c new file mode 100644 index 0000000..18dc0c1 --- /dev/null +++ b/src/mainboard/apple/imac11_2/hda_verb.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0272, /* Codec Vendor / Device ID: Realtek ALC272X */ + 0x10250379, /* Subsystem ID */ + 0, /* Number of 4 dword sets */ +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/apple/imac11_2/romstage.c b/src/mainboard/apple/imac11_2/romstage.c new file mode 100644 index 0000000..1104045 --- /dev/null +++ b/src/mainboard/apple/imac11_2/romstage.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <northbridge/intel/ironlake/ironlake.h> +#include <southbridge/intel/ibexpeak/pch.h> +#include <stdint.h> + +/* Seems copied from Lenovo Thinkpad x201, might be wrong */ +const struct southbridge_usb_port mainboard_usb_ports[] = { + /* Enabled, Current table lookup index, OC map */ + { 1, IF1_557, 0 }, + { 1, IF1_55F, 1 }, + { 1, IF1_74B, 3 }, + { 1, IF1_74B, 3 }, + { 1, IF1_557, 3 }, + { 1, IF1_14B, 3 }, + { 1, IF1_74B, 3 }, + { 1, IF1_74B, 3 }, + { 1, IF1_74B, 4 }, + { 1, IF1_74B, 5 }, + { 1, IF1_55F, 7 }, + { 1, IF1_55F, 7 }, + { 1, IF1_557, 7 }, + { 1, IF1_55F, 7 }, +}; + +void mainboard_pre_raminit(void) +{ +} + +void mainboard_get_spd_map(u8 *spd_addrmap) +{ + spd_addrmap[0] = 0x50; + spd_addrmap[2] = 0x52; +}