Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45941 )
Change subject: soc/intel/xeon_sp/cpx: corrrect GSI bases for IO APICs ......................................................................
Patch Set 2: Code-Review+1
(2 comments)
https://review.coreboot.org/c/coreboot/+/45941/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45941/2//COMMIT_MSG@7 PS2, Line 7: corrrect typo: remove one `r` in `rrr`
https://review.coreboot.org/c/coreboot/+/45941/2/src/soc/intel/xeon_sp/cpx/a... File src/soc/intel/xeon_sp/cpx/acpi.c:
https://review.coreboot.org/c/coreboot/+/45941/2/src/soc/intel/xeon_sp/cpx/a... PS2, Line 190: int gsi_bases[] = { 0, 0x78, 0x80, 0x28, 0x88, 0x90, 0x98, 0xA0, 0xA8, 0xB0 }; How have these values been determined?