[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/cannonlake: Support different SPD read type for each slot

[Paul Fagerburg (Code Review)]

Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32513 )

Change subject: soc/intel/cannonlake: Support different SPD read type for each slot
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Patch Set 10: Code-Review+1

(1 comment)

https://review.coreboot.org/#/c/32513/10/src/mainboard/google/hatch/romstage... 
File src/mainboard/google/hatch/romstage.c:

https://review.coreboot.org/#/c/32513/10/src/mainboard/google/hatch/romstage... 
PS10, Line 55: 	is_single_ch_mem = gpio_get(GPP_F2);
nit: please add a #define above (with GPIO_MEM_CONFIG_[0:3]) instead of using GPP_F2 here.