Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52782 )
Change subject: soc/intel/common/block: Add definition for NAF_VWE bit for PAD_CFG0 reg ......................................................................
soc/intel/common/block: Add definition for NAF_VWE bit for PAD_CFG0 reg
Earlier we did not have definition for BIT27 for PAD_CFG0 register, we will use this BIT to enable "virtual wire messaging for native function" If this bit is enabled, whenever change is detected on the pad, virtual wire message is generated and sent to destination set by native function. This bit must be set while enabling CPU PCIe root port programming for ADL and thus defining a new macro to set native pad function along with NAF_VWE bit to make GPIO programming easier from coreboot.
BUG=None BRANCH=None TEST=Code compilation works fine and if we use this macro to program GPIO, proper bit is getting set in PAD_CFG register
Change-Id: I732e68b413eb01b8ae1a4927836762c8875b73d2 Signed-off-by: Maulik V Vaghela maulik.v.vaghela@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/52782 Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Reviewed-by: Subrata Banik subrata.banik@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 1 file changed, 8 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index 2d6f62a..e5a536d 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -35,6 +35,7 @@ #define PAD_CFG0_TRIG_EDGE_SINGLE (1 << 25) /* controlled by RX_INVERT*/ #define PAD_CFG0_TRIG_OFF (2 << 25) #define PAD_CFG0_TRIG_EDGE_BOTH (3 << 25) +#define PAD_CFG0_NAFVWE_ENABLE (1 << 27) #define PAD_CFG0_RXRAW1_MASK (1 << 28) #define PAD_CFG0_RXPADSTSEL_MASK (1 << 29) #define PAD_CFG0_RESET_MASK (3 << 30) @@ -215,6 +216,13 @@ PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
+/* Native function configuration with "native function virtual wire + messaging enable (NAFVWE_ENABLE)" */ +#define PAD_CFG_NF_VWEN(pad, pull, rst, func) \ + _PAD_CFG_STRUCT(pad, \ + PAD_RESET(rst) | PAD_FUNC(func) | PAD_CFG0_NAFVWE_ENABLE,\ + PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE)) + /* General purpose output, no pullup/down. */ #define PAD_CFG_GPO(pad, val, rst) \ _PAD_CFG_STRUCT(pad, \