Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39346 )
Change subject: soc/intel/tigerlake: Add processor power limits control support ......................................................................
Patch Set 7:
(6 comments)
https://review.coreboot.org/c/coreboot/+/39346/5/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/39346/5/src/soc/intel/tigerlake/chi... PS5, Line 174: psys_pmax
We have plan to use this once closed system available.
Done
https://review.coreboot.org/c/coreboot/+/39346/5/src/soc/intel/tigerlake/cpu... File src/soc/intel/tigerlake/cpu.c:
https://review.coreboot.org/c/coreboot/+/39346/5/src/soc/intel/tigerlake/cpu... PS5, Line 218: MCH_DDR_POWER_LIMIT_LO
This is the same as per other platform implementation.
Done
https://review.coreboot.org/c/coreboot/+/39346/5/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/msr.h:
https://review.coreboot.org/c/coreboot/+/39346/5/src/soc/intel/tigerlake/inc... PS5, Line 23:
Remove tap
Done
https://review.coreboot.org/c/coreboot/+/39346/5/src/soc/intel/tigerlake/inc... PS5, Line 25:
Remove tap
Done
https://review.coreboot.org/c/coreboot/+/39346/5/src/soc/intel/tigerlake/sys... File src/soc/intel/tigerlake/systemagent.c:
https://review.coreboot.org/c/coreboot/+/39346/5/src/soc/intel/tigerlake/sys... PS5, Line 86: 28
Could we get a symbolic constant for this? Something like MOBILE_SKU_PL1_TIME_SEC ?
Ack
https://review.coreboot.org/c/coreboot/+/39346/7/src/soc/intel/tigerlake/sys... File src/soc/intel/tigerlake/systemagent.c:
https://review.coreboot.org/c/coreboot/+/39346/7/src/soc/intel/tigerlake/sys... PS7, Line 84: /* Configure turbo power limits 1ms after reset complete bit */
Is that documented in some datasheet?
this documented in EDS (External design specification) document