Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87086?usp=email )
Change subject: src/vendorcode/amd/fsp: Update for glinda ......................................................................
src/vendorcode/amd/fsp: Update for glinda
Update params for Glinda SoC according to glinda FSP.
TEST=Build & boot AMD birman plus board & make sure dmidecode -t 17 shows more accurate info.
Signed-off-by: Maximilian Brune maximilian.brune@9elements.com Change-Id: I110039e160ada8899e3a414fcf32ee8236b510b4 --- M src/vendorcode/amd/fsp/common/dmi_info.h M src/vendorcode/amd/fsp/glinda/soc_dmi_info.h 2 files changed, 59 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/87086/1
diff --git a/src/vendorcode/amd/fsp/common/dmi_info.h b/src/vendorcode/amd/fsp/common/dmi_info.h index 390732d..1f94a32 100644 --- a/src/vendorcode/amd/fsp/common/dmi_info.h +++ b/src/vendorcode/amd/fsp/common/dmi_info.h @@ -157,7 +157,11 @@ OUT UINT16 Speed; ///< Identifies the speed of the device, in megahertz (MHz). OUT UINT64 ManufacturerIdCode; ///< Manufacturer ID code. OUT CHAR8 SerialNumber[9]; ///< Serial Number. +#if CONFIG(SOC_AMD_GLINDA) + OUT CHAR8 PartNumber[31]; ///< Part Number. +#else OUT CHAR8 PartNumber[21]; ///< Part Number. +#endif OUT UINT8 Attributes; ///< Bits 7-4: Reserved, Bits 3-0: rank. OUT UINT32 ExtSize; ///< Extended Size. OUT UINT16 ConfigSpeed; ///< Configured memory clock speed @@ -183,8 +187,58 @@ #endif } __packed TYPE17_DMI_INFO;
+/// DMI Type 19 - Memory Array Mapped Address +typedef struct { + OUT UINT32 StartingAddr; ///< The physical address, in kilobytes, + ///< of a range of memory mapped to the + ///< specified physical memory array. + OUT UINT32 EndingAddr; ///< The physical ending address of the + ///< last kilobyte of a range of addresses + ///< mapped to the specified physical memory array. + OUT UINT16 MemoryArrayHandle; ///< The handle, or instance number, associated + ///< with the physical memory array to which this + ///< address range is mapped. + OUT UINT8 PartitionWidth; ///< Identifies the number of memory devices that + ///< form a single row of memory for the address + ///< partition defined by this structure. + OUT UINT64 ExtStartingAddr; ///< The physical address, in bytes, of a range of + ///< memory mapped to the specified Physical Memory Array. + OUT UINT64 ExtEndingAddr; ///< The physical address, in bytes, of a range of + ///< memory mapped to the specified Physical Memory Array. +} TYPE19_DMI_INFO; + +///DMI Type 20 - Memory Device Mapped Address +typedef struct { + OUT UINT32 StartingAddr; ///< The physical address, in kilobytes, of a range + ///< of memory mapped to the referenced Memory Device. + OUT UINT32 EndingAddr; ///< The handle, or instance number, associated with + ///< the Memory Device structure to which this address + ///< range is mapped. + OUT UINT16 MemoryDeviceHandle; ///< The handle, or instance number, associated with + ///< the Memory Device structure to which this address + ///< range is mapped. + OUT UINT16 MemoryArrayMappedAddressHandle; ///< The handle, or instance number, associated + ///< with the Memory Array Mapped Address structure to + ///< which this device address range is mapped. + OUT UINT8 PartitionRowPosition; ///< Identifies the position of the referenced Memory + ///< Device in a row of the address partition. + OUT UINT8 InterleavePosition; ///< The position of the referenced Memory Device in + ///< an interleave. + OUT UINT8 InterleavedDataDepth; ///< The maximum number of consecutive rows from the + ///< referenced Memory Device that are accessed in a + ///< single interleaved transfer. + OUT UINT64 ExtStartingAddr; ///< The physical address, in bytes, of a range of + ///< memory mapped to the referenced Memory Device. + OUT UINT64 ExtEndingAddr; ///< The physical ending address, in bytes, of the last of + ///< a range of addresses mapped to the referenced Memory Device. +} TYPE20_DMI_INFO; + /// Collection of pointers to the DMI records typedef struct { OUT TYPE16_DMI_INFO T16; ///< Type 16 struc OUT TYPE17_DMI_INFO T17[AGESA_STRUCT_SOCKET_COUNT][AGESA_STRUCT_CHANNELS_PER_SOCKET][AGESA_STRUCT_DIMMS_PER_CHANNEL]; ///< Type 17 struc +#if CONFIG(SOC_AMD_GLINDA) + OUT TYPE19_DMI_INFO T19[AGESA_STRUCT_T19_REGION_SUPPORTED]; + OUT TYPE20_DMI_INFO T20[AGESA_STRUCT_SOCKET_COUNT][AGESA_STRUCT_CHANNELS_PER_SOCKET][AGESA_STRUCT_DIMMS_PER_CHANNEL][AGESA_STRUCT_T20_REGION_SUPPORTED]; ///< Type 20 struc +#endif } DMI_INFO; diff --git a/src/vendorcode/amd/fsp/glinda/soc_dmi_info.h b/src/vendorcode/amd/fsp/glinda/soc_dmi_info.h index 08f5f5c..f854059 100644 --- a/src/vendorcode/amd/fsp/glinda/soc_dmi_info.h +++ b/src/vendorcode/amd/fsp/glinda/soc_dmi_info.h @@ -2,15 +2,16 @@
/* * These definitions are used to describe memory modules physical layout - * TODO: Update for Glinda */
#ifndef SOC_DMI_INFO_H #define SOC_DMI_INFO_H
-#define AGESA_STRUCT_SOCKET_COUNT 2 ///< Number of sockets in AGESA FSP DMI T17 table -#define AGESA_STRUCT_CHANNELS_PER_SOCKET 8 ///< Channels per socket in AGESA FSP DMI T17 table -#define AGESA_STRUCT_DIMMS_PER_CHANNEL 4 ///< DIMMs per channel in AGESA FSP DMI T17 table +#define AGESA_STRUCT_SOCKET_COUNT 4 ///< Number of sockets in AGESA FSP DMI T17 table +#define AGESA_STRUCT_CHANNELS_PER_SOCKET 16 ///< Channels per socket in AGESA FSP DMI T17 table +#define AGESA_STRUCT_DIMMS_PER_CHANNEL 2 ///< DIMMs per channel in AGESA FSP DMI T17 table +#define AGESA_STRUCT_T19_REGION_SUPPORTED 3 ///< Max SMBIOS T19 Memory Region count +#define AGESA_STRUCT_T20_REGION_SUPPORTED 3 ///< Max SMBIOS T20 Memory Region count
#define SMBIOS_3_2_3_3_SUPPORT 1