[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Move acpi_sci_irq() to acpi.c

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52462 )

Change subject: soc/intel/skylake: Move acpi_sci_irq() to acpi.c
......................................................................

soc/intel/skylake: Move acpi_sci_irq() to acpi.c

Change-Id: I8bc170bd715e13d46fcedc0f796e2a99786791c0
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52462
Tested-by: build bot (Jenkins) 
Reviewed-by: Tim Wawrzynczak 
Reviewed-by: Michael Niewöhner 
Reviewed-by: Frans Hendriks 
---
M src/soc/intel/skylake/acpi.c
M src/soc/intel/skylake/fadt.c
M src/soc/intel/skylake/include/soc/acpi.h
M src/soc/intel/skylake/include/soc/pm.h
M src/soc/intel/skylake/pmutil.c
5 files changed, 31 insertions(+), 31 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Frans Hendriks: Looks good to me, approved
  Tim Wawrzynczak: Looks good to me, approved
  Michael Niewöhner: Looks good to me, approved

diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c
index 3434aac..51fea18 100644
--- a/src/soc/intel/skylake/acpi.c
+++ b/src/soc/intel/skylake/acpi.c
@@ -475,6 +475,34 @@
    return current;
 }

+int acpi_sci_irq(void)
+{
+	int scis = pci_read_config32(PCH_DEV_PMC, ACTL) & SCI_IRQ_SEL;
+	int sci_irq = 9;
+
+	/* Determine how SCI is routed. */
+	switch (scis) {
+	case SCIS_IRQ9:
+	case SCIS_IRQ10:
+	case SCIS_IRQ11:
+		sci_irq = scis - SCIS_IRQ9 + 9;
+		break;
+	case SCIS_IRQ20:
+	case SCIS_IRQ21:
+	case SCIS_IRQ22:
+	case SCIS_IRQ23:
+		sci_irq = scis - SCIS_IRQ20 + 20;
+		break;
+	default:
+		printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n");
+		sci_irq = 9;
+		break;
+	}
+
+	printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq);
+	return sci_irq;
+}
+
 unsigned long acpi_madt_irq_overrides(unsigned long current)
 {
    int sci = acpi_sci_irq();
diff --git a/src/soc/intel/skylake/fadt.c b/src/soc/intel/skylake/fadt.c
index c8e4ec4..3e60216 100644
--- a/src/soc/intel/skylake/fadt.c
+++ b/src/soc/intel/skylake/fadt.c
@@ -2,6 +2,7 @@

#include <acpi/acpi.h>
 #include <cpu/x86/smm.h>
+#include <soc/acpi.h>
 #include <soc/iomap.h>
 #include <soc/pm.h>
 #include "chip.h"
diff --git a/src/soc/intel/skylake/include/soc/acpi.h b/src/soc/intel/skylake/include/soc/acpi.h
index e12a748..683a504 100644
--- a/src/soc/intel/skylake/include/soc/acpi.h
+++ b/src/soc/intel/skylake/include/soc/acpi.h
@@ -11,6 +11,8 @@
 #define PSS_LATENCY_TRANSITION		10
 #define PSS_LATENCY_BUSMASTER		10

+/* Return the selected ACPI SCI IRQ */
+int acpi_sci_irq(void);
 unsigned long acpi_madt_irq_overrides(unsigned long current);
 unsigned long northbridge_write_acpi_tables(const struct device *,
    unsigned long current, struct acpi_rsdp *);
diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h
index cd5c43e..a577724 100644
--- a/src/soc/intel/skylake/include/soc/pm.h
+++ b/src/soc/intel/skylake/include/soc/pm.h
@@ -155,9 +155,6 @@
    uint32_t prev_sleep_state;
 } __packed;

-/* Return the selected ACPI SCI IRQ */
-int acpi_sci_irq(void);
-
 /* Get base address PMC memory mapped registers. */
 uint8_t *pmc_mmio_regs(void);

diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c
index 906a1cf..115a9e5 100644
--- a/src/soc/intel/skylake/pmutil.c
+++ b/src/soc/intel/skylake/pmutil.c
@@ -113,34 +113,6 @@
    return gpe_sts_bits;
 }

-int acpi_sci_irq(void)
-{
-	int scis = pci_read_config32(PCH_DEV_PMC, ACTL) & SCI_IRQ_SEL;
-	int sci_irq = 9;
-
-	/* Determine how SCI is routed. */
-	switch (scis) {
-	case SCIS_IRQ9:
-	case SCIS_IRQ10:
-	case SCIS_IRQ11:
-		sci_irq = scis - SCIS_IRQ9 + 9;
-		break;
-	case SCIS_IRQ20:
-	case SCIS_IRQ21:
-	case SCIS_IRQ22:
-	case SCIS_IRQ23:
-		sci_irq = scis - SCIS_IRQ20 + 20;
-		break;
-	default:
-		printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n");
-		sci_irq = 9;
-		break;
-	}
-
-	printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq);
-	return sci_irq;
-}
-
 uint8_t *pmc_mmio_regs(void)
 {
    uint32_t reg32;