[coreboot-gerrit] Change in coreboot[master]: [TESTONLY]cpu/intel/p4-netburst: skip caching rom on model_fxx

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27133

Change subject: [TESTONLY]cpu/intel/p4-netburst: skip caching rom on model_fxx
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[TESTONLY]cpu/intel/p4-netburst: skip caching rom on model_fxx

Vendor does this too...

Change-Id: I1df84ad55e2d8d6d4e8dca10125131b5f525f0d7
Signed-off-by: Arthur Heymans 
---
M src/cpu/intel/car/p4-netburst/cache_as_ram.S
1 file changed, 7 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/27133/1

diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
index 58782b9..cd55ad4 100644
--- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S
+++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
@@ -315,6 +315,11 @@
    orl	$CR0_CacheDisable, %eax
    movl	%eax, %cr0

+	movl	$1, %eax
+	cpuid
+	cmp	$0x6, %ah
+	jne	skip_cache_rom
+
    /* Enable cache for our code in Flash because we do XIP here */
    movl	$MTRR_PHYS_BASE(1), %ecx
    xorl	%edx, %edx
@@ -332,6 +337,8 @@
    movl	$(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
    wrmsr

+skip_cache_rom:
+
    post_code(0x2e)
    /* Enable cache. */
    movl	%cr0, %eax