Attention is currently required from: Zhaoqing Jiu.
Hello Zhaoqing Jiu,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/86551?usp=email
to review the following change.
Change subject: soc/mediatek/mt8196: Save HW protect temperature to SRAM ......................................................................
soc/mediatek/mt8196: Save HW protect temperature to SRAM
It will restore the HW protection settings based on the data saved in the SRAM, after the system suspends and resumes.
BRANCH=rauru BUG=b:389026545 TEST=Boot up and check temperature in coreboot log: [INFO ] [LVTS_MSR] ts0 msr_all=141d0, msr_temp=16848, temp=41086 [INFO ] lvts_tscpu_thermal_read_tc_temp order 0 ts_name 0 temp 41086 rg_temp 41073(42059) [INFO ] [LVTS_MSR] ts1 msr_all=141e3, msr_temp=16867, temp=41540 [INFO ] lvts_tscpu_thermal_read_tc_temp order 1 ts_name 1 temp 41540 rg_temp 41526(42523) [INFO ] [LVTS_MSR] ts2 msr_all=14199, msr_temp=16793, temp=39772[0m [INFO ] lvts_tscpu_thermal_read_tc_temp order 2 ts_name 2 temp 39772 rg_temp 39760(40715) [INFO ] [LVTS_MSR] ts3 msr_all=141c2, msr_temp=16834, temp=40751 [INFO ] lvts_tscpu_thermal_read_tc_temp order 3 ts_name 3 temp 40751 rg_temp 40739(41717) [INFO ] [LVTS_MSR] ts4 msr_all=141d0, msr_temp=16848, temp=41086 [INFO ] lvts_tscpu_thermal_read_tc_temp order 0 ts_name 4 temp 41086 rg_temp 41073(42059) [INFO ] [LVTS_MSR] ts5 msr_all=141b3, msr_temp=16819, temp=40393 [INFO ] lvts_tscpu_thermal_read_tc_temp order 1 ts_name 5 temp 40393 rg_temp 40380(41350) [INFO ] [LVTS_MSR] ts6 msr_all=14194, msr_temp=16788, temp=39652 [INFO ] lvts_tscpu_thermal_read_tc_temp order 2 ts_name 6 temp 39652 rg_temp 39641(40593) [INFO ] [LVTS_MSR] ts7 msr_all=14186, msr_temp=16774, temp=39318 [INFO ] lvts_tscpu_thermal_read_tc_temp order 3 ts_name 7 temp 39318 rg_temp 39307(40251)
Signed-off-by: Zhaoqing Jiu zhaoqing.jiu@mediatek.corp-partner.google.com Change-Id: Ib714c297871132907e286536c4b3aea1532f3869 --- M src/soc/mediatek/mt8196/include/soc/thermal.h M src/soc/mediatek/mt8196/thermal.c M src/soc/mediatek/mt8196/thermal_sram.c 3 files changed, 34 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/86551/1
diff --git a/src/soc/mediatek/mt8196/include/soc/thermal.h b/src/soc/mediatek/mt8196/include/soc/thermal.h index 6d2b523..1517b37 100644 --- a/src/soc/mediatek/mt8196/include/soc/thermal.h +++ b/src/soc/mediatek/mt8196/include/soc/thermal.h @@ -5,5 +5,7 @@
void thermal_sram_init(void); void thermal_init(void); +void thermal_write_reboot_temp_sram(int value); +void thermal_write_reboot_msr_sram(int idx, int value);
#endif /* SOC_MEDIATEK_MT8196_THERMAL_H */ diff --git a/src/soc/mediatek/mt8196/thermal.c b/src/soc/mediatek/mt8196/thermal.c index 001cd06..be7fece 100644 --- a/src/soc/mediatek/mt8196/thermal.c +++ b/src/soc/mediatek/mt8196/thermal.c @@ -575,12 +575,14 @@ write32p(AP_RST_CLR, BIT(11)); }
-static void lvts_set_tc_trigger_hw_protect(const struct lvts_thermal_controller *tc) +static void lvts_set_tc_trigger_hw_protect(unsigned int tc_num) { int d_index, i; uint32_t raw_high; uint16_t raw; enum lvts_sensor ts_name; + int tc_index = 0xFF; + const struct lvts_thermal_controller *tc = &lvts_tscpu_g_tc[tc_num];
if (tc->dominator_ts_idx < tc->ts_number) { d_index = tc->dominator_ts_idx; @@ -601,6 +603,16 @@ raw = lvts_temp_to_raw(tc->reboot_temperature, ts_name); raw_high = MAX(raw_high, raw); } + if (tc_num == LVTS_AP_CONTROLLER0) + tc_index = 0; + else if (tc_num == LVTS_AP_CONTROLLER1) + tc_index = 1; + + if (tc_index != 0xff) { + thermal_write_reboot_msr_sram(tc_index, raw_high); + if (tc_index == 0) + thermal_write_reboot_temp_sram(tc->reboot_temperature); + }
setbits32(&tc->regs->lvtsprotctl_0, 0x3FFF); /* disable trigger SPM interrupt */ @@ -623,11 +635,10 @@ printk(BIOS_INFO, "===== %s begin ======\n", __func__);
for (i = 0; i < ARRAY_SIZE(lvts_tscpu_g_tc); i++) { - const struct lvts_thermal_controller *tc = &lvts_tscpu_g_tc[i]; - if (tc->ctrl_on_off == CTRL_OFF) + if ((&lvts_tscpu_g_tc[i])->ctrl_on_off == CTRL_OFF) continue;
- lvts_set_tc_trigger_hw_protect(tc); + lvts_set_tc_trigger_hw_protect(i); } }
diff --git a/src/soc/mediatek/mt8196/thermal_sram.c b/src/soc/mediatek/mt8196/thermal_sram.c index 5509792..23500cb 100644 --- a/src/soc/mediatek/mt8196/thermal_sram.c +++ b/src/soc/mediatek/mt8196/thermal_sram.c @@ -7,6 +7,9 @@ /* SRAM for Thermal */ #define THERMAL_SRAM_BASE (_mcufw_reserved + 0x1000) #define THERMAL_SRAM_LEN 0x400 +#define THERMAL_REBOOT_TEMP_SRAM_OFFSET 0x39c +#define THERMAL_REBOOT_MSR_SRAM_OFFSET 0x340 +#define THERMAL_REBOOT_MSR_SRAM_LEN (6 * 4)
static void thermal_cls_sram(void) { @@ -59,3 +62,17 @@ thermal_stat_cls_sram(); thermal_gpu_stat_cls_sram(); } + +void thermal_write_reboot_temp_sram(int value) +{ + write32(THERMAL_SRAM_BASE + THERMAL_REBOOT_TEMP_SRAM_OFFSET, value); +} + +void thermal_write_reboot_msr_sram(int idx, int value) +{ + unsigned int offset = 0; + if ((idx * 4) < THERMAL_REBOOT_MSR_SRAM_LEN) { + offset = THERMAL_REBOOT_MSR_SRAM_OFFSET + idx * 4; + write32(THERMAL_SRAM_BASE + offset, value); + } +}